ATSAMB11XR datasheet(38/87 Pages) MICROCHIP

38 / 87 page

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MUX1: any option from the MEGAMUX table can be selected, for example, it can be a quad_dec,

pwm, or any of the other functions listed in the MEGAMUX table

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MUX2: the pin functions as UART1 TXD; this can be also achieved with the MUX1 option via

MEGAMUX, but the MUX2 option allows a shortcut for the recommended pinout

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MUX3: this option is not used and thus defaults to the GPIO option (same as MUX0)

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MUX4: the pin functions as SPI1 MOSI (this option is not available through MEGAMUX)

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MUX5: the pin functions as SPI0 MOSI (this option is not available through MEGAMUX)

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MUX6: the pin functions as SPI FLASH SCK (this option is not available through MEGAMUX)

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MUX7: the pin functions as bit 3 of the test output bus, giving access to various debug signals

9.2

I2C Master/Slave Interface

9.2.1

Description

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA provides an I2C Interface that can be configured as

Slave or Master. I2C Interface is a two-wire serial interface consisting of a serial data line (SDA) and a

serial clock line (SCL). The ATSAMB11-XR2100A and ATSAMB11-ZR210CA I2C support I2C bus Version

2.1 - 2000 and can operate in the following speed modes:

•

Standard mode (100 kb/s)

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Fast mode (400 kb/s)

•

High-speed mode (3.4 Mb/s)

The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while

the SCL line is low, except for STOP and START conditions. The I2C peripheral does not support

repeated start condition. The output drivers are open-drain to perform wire-AND functions on the bus.

The maximum number of devices on the bus are limited by only the maximum capacitance specification

of 400 pF. Data is transmitted in byte packages.

For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Ver 2.1”.

9.3

SPI Master/Slave Interface

9.3.1

Description

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA provides a Serial Peripheral Interface (SPI) that

can be configured as Master or Slave. The SPI Interface pins are mapped, as illustrated in the following

figure. The SPI Interface is a full-duplex slave-synchronous serial interface. When the SPI is not selected,

i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master

and other serial-slave devices. When the serial slave is not selected, its transmitted data output is

buffered, resulting in a high impedance drive onto the serial master receive line. The SPI Slave interface

responds to a protocol that allows an external host to read or write any register in the chip as well as

initiate DMA transfers.

Table 9-3. SPI Interface Pin Mapping

Pin Name

SPI Function

SSN

Active Low Slave Select

SCK

Serial Clock

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 38

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