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ATSAMB11XR датащи(PDF) 42 Page - Microchip Technology |
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ATSAMB11XR датащи(HTML) 42 Page - Microchip Technology |
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42 / 87 page ![]() 9.6.2 Timing The ADC timing is shown in Figure SAR ADC Timing. The input signal is sampled twice, in the first sampling cycle the input range is defined either to be above reference voltage or below it and in the second sampling instant the ADC start its normal operation. The ADC takes two sampling instants and N-1 conversion cycle (N=ADC resolution) and one cycle to sample the data out. Therefore, for the 11-bit resolution, it takes 13 clock cycles to do one Sample conversion. The Input clock equals N+2 the sampling clock frequency (N is the ADC resolution). CONV signal : Gives indication about end of conversion. SAMPL : The input signal is sampled when this signal is high. RST ENG : When High SAR Engine is in reset mode (SAR engine output is set to mid-scale). Figure 9-4. SAR ADC Timing 9.6.3 GPIOs The 23 General Purpose Input/Output (GPIO) pins, labeled as LP_GPIO, 4 GPIO_MS, and 3 AO_GPIO, are available to allow for application specific functions. Each GPIO pin can be programmed as an input or as an output. The host or internal processor can program the output values. LP_GPIO are digital interface pins, GPIO_MS are mixed signal/analog interface pins, and AO_GPIO is an always-on digital interface pin. AO_GPIO can be used as a wake-up source from Ultra_Low_Power mode. The LP_GPIO have interrupt capability, only during inactive/standby mode. In sleep mode, they are turned off to save power consumption. 9.7 Software Programmable Timer and Pulse Width Modulator The ATSAMB11-XR2100A and ATSAMB11-ZR210CA contain four individually configurable pulse width modulator (PWM) blocks to provide external control voltages. The base frequency of the PWM block (fPWM_base) is derived from the XO clock (26 MHz) or the RC oscillator followed by a programmable divider. The frequency of each PWM pulse (fPWM ) is programmable in steps according to the following relationship: ��������=��������_�������� 64*2�� ��=0,1,2,…,8 The duty cycle of each PWM signal is configurable with 10-bit resolution (minimum duty cycle is 1/1024 and the maximum is 1023/1024). ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 42 |
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