AD9683 datasheet(30/45 Pages) AD

30 / 45 page

Data Sheet

AD9683

Rev. D | Page 29 of 44

–0.5

0.5

ULS

PERIOD1: HISTOGRAM

6000

7000

–10

TIME (ps)

5000

4000

1000

2000

3000

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–100

–200

100

200

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ AT BER1: BATHTUB

EYE: ALL BITS OFFSET: 0

ULS: 7000; 993329 TOTAL: 7000; 993329

Figure 64. AD9683 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps

–0.5

0.5

ULS

PERIOD1: HISTOGRAM

6000

7000

–10

TIME (ps)

5000

4000

1000

2000

3000

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–50

–150

–250

250

150

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ AT BER1: BATHTUB

EYE: ALL BITS OFFSET: 0.0018

ULS: 8000; 673330 TOTAL: 8000; 673330

Figure 65. AD9683 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 3.4 Gbps

ADC OVERRANGE AND GAIN CONTROL

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overflow indicator provides delayed information on

the state of the analog input that is of limited value in preventing

clipping. Therefore, it is helpful to have a programmable threshold

below full scale that allows time to reduce the gain before the

clip occurs. In addition, because input signals can have significant

slew rates, latency of this function is of concern.

Using the SPI port, the user can provide a threshold above which

the FD output is active. Bit 0 of Address 0x45 enables the fast

detect feature. Address 0x47 to Address 0x4A allow the user to

set the threshold levels. As long as the signal is below the selected

threshold, the FD output remains low. In this mode, the magnitude

of the data is considered in the calculation of the condition, but

the sign of the data is not considered. The threshold detection

responds identically to positive and negative signals outside the

desired range (magnitude).

ADC Overrange (OR)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 36 ADC clock cycles. An overrange at the

input is indicated by this bit 36 clock cycles after it occurs.

Gain Switching

The AD9683 includes circuitry that is useful in applications

either where large dynamic ranges exist or where gain ranging

amplifiers are employed. This circuitry allows digital thresholds

to be set such that an upper threshold and a lower threshold can

be programmed.

One such use is to detect when an ADC is about to reach full

scale with a particular input condition. The result is to provide

an indicator that can be used to quickly insert an attenuator that

prevents ADC overdrive.

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