AD9683

Data Sheet

Rev. D | Page 6 of 44

AD9683-170

AD9683-250

Temperature

Min

Typ

Max

Min

Typ

Max

Unit

TWO-TONE SFDR

25°C

87

87

dBc

25°C

1000

1000

MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions.

2

Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p

full-scale input range, DCS enabled, default SPI, unless otherwise noted.

Table 3.

Parameter

Temperature

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Input CLK± Clock Rate

Full

40

625

MHz

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage

Full

0.3

3.6

V p-p

Input Voltage Range

Full

AGND

AVDD

V

Input Common-Mode Range

Full

0.9

1.4

V

High Level Input Current

Full

0

+60

µA

Low Level Input Current

Full

−60

0

µA

Input Capacitance

Full

4

pF

Input Resistance

Full

8

10

12

kΩ

RF CLOCK INPUT (RFCLK)

RF Clock Rate

Full

500

1500

MHz

Logic Compliance

CMOS/LVDS/LVPECL

Internal Bias

Full

0.9

V

Input Voltage Range

Full

AGND

AVDD

V

High Input Voltage Level

Full

1.2

AVDD

V

Low Input Voltage Level

Full

AGND

0.6

V

High Level Input Current

Full

0

+150

µA

Low Level Input Current

Full

−150

0

µA

Input Capacitance

Full

1

pF

Input Resistance (AC-Coupled)

Full

8

10

12

kΩ

SYNCIN INPUTS (SYNCINB+/SYNCINB−)

Logic Compliance

CMOS/LVDS

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage Range

Full

0.3

3.6

V p-p

Input Voltage Range

Full

DGND

DVDD

V

Input Common-Mode Range

Full

0.9

1.4

V

High Level Input Current

Full

−5

+5

µA

Low Level Input Current

Full

−10

+10

µA

Input Capacitance

Full

1

pF

Input Resistance

Full

12

16

20

kΩ