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Data Sheet

AD9683

Rev. D | Page 23 of 44

0.1µF

LVPECL

DRIVER

AD9515

127Ω

VDD

82.5Ω

127Ω

82.5Ω

CLOCK INPUT

RFCLK

ADC

Ω Tx LINE

0.1µF

Ω

Figure 56. Differential PECL RF Clock Input Circuit

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input frequency

(fIN) due to jitter (tJ) can be calculated by

SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10

)

(

SNR

−

]

In the equation, the rms aperture jitter represents the root-mean-

square of all jitter sources, which include the clock input, the

analog input signal, and the ADC aperture jitter specification. IF

undersampling applications are particularly sensitive to jitter,

as shown in Figure 57.

100

1000

INPUT FREQUENCY (MHz)

0.05ps

0.2ps

0.5ps

1ps

1.5ps

MEASURED

Figure 57. AD9683-250 SNR vs. Input Frequency and Jitter

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9683. Separate the

power supplies for the clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

Low jitter, crystal controlled oscillators make the best clock sources.

If the clock is generated from another type of source (by gating,

dividing, or another method), retime it using the original clock at

the last step.

Refer to the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, and the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter, for

more information about jitter performance as it relates to ADCs.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 58, the power dissipated by the AD9683 is

proportional to its sample rate. The data in Figure 58 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section. IDVDD in Figure 58 is a

summation of IDVDD and IDRVDD.

0.05

0.10

0.15

0.20

0.25

0.1

0.2

0.3

0.4

0.5

85 100 115 130 145 160 175 190 205 220 235 250

ENCODE FREQUENCY (MSPS)

IAVDD

TOTAL POWER

IDVDD

Figure 58. AD9683-250 Power vs. Encode Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9683 is placed in power-down mode.

In this state, the ADC typically dissipates about 9 mW. Asserting the

PDWN pin low returns the AD9683 to its normal operating mode.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Descriptions section and the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI, for additional details.

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