AD9683 datasheet(29/45 Pages) AD

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AD9683

Data Sheet

Rev. D | Page 28 of 44

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the JESD204B

specification. The 14-bit word requires two octets to transmit all

the data. The two octets (MSB and LSB), where F = 2, make up

a frame. During normal operating conditions, frame alignment

is monitored via alignment characters, which are inserted under

certain conditions at the end of a frame. Table 14 summarizes the

conditions for character insertion along with the expected characters

under the various operation modes. If lane synchronization is

enabled, the replacement character value depends on whether

the octet is at the end of a frame or at the end of a multiframe.

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replacement characters.

Digital Outputs and Timing

The AD9683 has differential digital outputs that power up by

default. The driver current is derived on chip and sets the output

current at each output equal to a nominal 3 mA. Each output

presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 600 mV p-p swing at the receiver

(see Figure 62). Alternatively, single-ended 50 Ω termination

can be used. When single-ended termination is used, the

termination voltage must be DRVDD/2; otherwise, ac coupling

capacitors can be used to terminate to any single-ended voltage.

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUT0+

DRVDD

VRXCM

SERDOUT0–

VCM = Rx VCM

OUTPUT SWING = 600mV p-p

0.1µF

RECEIVER

Figure 62. AC-Coupled Digital Output Termination Example

The AD9683 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common mode

of the digital output automatically biases itself to half the supply

of the AD9683 (that is, the common-mode voltage is 0.9 V for a

supply of 1.8 V) if a dc-coupled connection is used (see Figure 63).

For a receiver logic that is not within the bounds of the DRVDD

supply, use an ac-coupled connection. Simply place a 0.1 µF

capacitor on each output pin and derive a 100 Ω differential

termination close to the receiver side.

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

OUTPUT SWING = 600mV p-p

RECEIVER

SERDOUT0+

SERDOUT0–

Figure 63. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches, and that the differential output traces be

close together and at equal lengths.

Figure 64 shows an example of the digital output (default) data eye

and time interval error (TIE) jitter histogram and bathtub curve for

the AD9683 lane running at 5 Gbps.

Additional SPI options allow the user to further increase the output

driver voltage swing or enable preemphasis to drive longer trace

lengths (see Address 0x15 in Table 17). The power dissipation

of the DRVDD supply increases when this option is used. See the

Memory Map section for more details.

The format of the output data is twos complement by default.

To change the output data format to offset binary, see the

Memory Map section (Address 0x14 in Table 17).

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