AD9683 datasheet(35/45 Pages) AD

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AD9683

Data Sheet

Rev. D | Page 34 of 44

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the

chip configuration registers (Address 0x00 to Address 0x02);

the ADC functions registers, including setup, control, and test

(Address 0x08 to Address 0xA8); and the device update register

(Address 0xFF).

The memory map register table (see Table 17) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x14, the output

mode register, has a hexadecimal default value of 0x01. This means

that Bit 0 = 1, and the remaining bits are 0s. This setting is the

default output format value, which is twos complement. For

more information on this function and others, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI. This

application note details the functions controlled by Address 0x00

to Address 0x21 and Address 0xFF, with the exception of

Address 0x08 and Address 0x14. The remaining registers,

Address 0x08, Address 0x14, and Address 0x3A through

Address 0xA8, are documented in the Memory Map Register

Descriptions section.

Open and Reserved Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Write unused bits of

a valid address location with 0s. Writing to these locations is

required only when part of an address location is open (for

example, Address 0x18). If the entire address location is open

(for example, Address 0x13), do not write to this address location.

Default Values

After the AD9683 is reset, critical registers are loaded with default

values. The default values for the registers are given in the memory

map register table (see Table 17).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x09, Address 0x0B, Address 0x0D, Address 0x10,

Address 0x14, Address 0x18, Address 21, and Address 0x3A to

Address 0x4C are shadowed. Writes to these addresses do not

affect part operation until a transfer command is issued by

writing 0x01 to Address 0xFF, setting the transfer bit. This

allows these registers to be updated internally and simultaneously

when the transfer bit is set. The internal update takes place when

the transfer bit is set, and then the bit autoclears.

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