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Data Sheet

AD9683

Rev. D | Page 25 of 44

JESD204B Synchronization Details

The AD9683 is a JESD204B Subclass 1 device that establishes

synchronization of the link through two control signals, SYSREF

and SYNC, and typically a common device clock. SYSREF and

SYNC are common to all converter devices for alignment purposes

at the system level.

The synchronization process is accomplished over three phases:

code group synchronization (CGS), initial lane alignment sequence

(ILAS), and data transmission. If scrambling is enabled, the bits are

not actually scrambled until the data transmission phase, and

the CGS phase and ILAS phase do not use scrambling.

CGS Phase

In the CGS phase, the JESD204B transmit block transmits

/K28.5/ characters. The receiver (external logic device) must

locate /K28.5/ characters in its input data stream using clock

and data recovery (CDR) techniques.

When a certain number of consecutive /K28.5/ characters are

detected on the link lane, the receiver initiates a SYSREF edge

so that the AD9683 transmit data establishes a local multiframe

clock (LMFC) internally.

The SYSREF edge also resets any sampling edges within the ADC

to align sampling instances to the LMFC. This is important to

maintain synchronization across multiple devices.

The receiver or logic device deasserts the SYNC signal

(SYNCINB±), and the transmitter block begins the ILAS phase.

ILAS Phase

In the ILAS phase, the transmitter sends out a known pattern,

and the receiver aligns the lanes in the link and verifies the

parameters of the link.

The ILAS phase begins after SYNC has been deasserted (goes

high). The transmit block begins to transmit four multiframes.

Dummy samples are inserted between the required characters

so that full multiframes are transmitted. The four multiframes

include the following:

•

Multiframe 1 begins with an /R/ character [K28.0] and

ends with an /A/ character [K28.3].

•

Multiframe 2 begins with an /R/ character followed by a /Q/

[K28.4] character, followed by link configuration parameters

over 14 configuration octets (see Table 10), and ends with

an /A/ character.

•

Multiframe 3 is the same as Multiframe 1.

•

Multiframe 4 is the same as Multiframe 1.

Data Transmission Phase

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:

•

If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.

•

If scrambling is enabled and the last octet of the multiframe is

equal to 0x7C, or the last octet of a frame is equal to 0xFC.

Table 10. Fourteen Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Reserved, don’t care

FCHK[7:0]

Link Setup Parameters

The following sections demonstrate how to configure the AD9683

JESD204B interface. The steps to configure the output include

the following:

1. Disable the lane before changing the configuration.

2. Select a quick configuration option.

3. Configure detailed options.

4. Check FCHK, the checksum of the JESD204B interface

parameters.

5. Set additional digital output configuration options.

6. Re-enable the lane.

Disable Lane Before Changing Configuration

Before modifying the JESD204B link parameters, disable the link

and hold it in reset. This is accomplished by writing Logic 1 to

Address 0x5F, Bit 0.

Configure Detailed Options

Configure the tail bits and control bits as follows.

•

With N’ = 16 and N = 14, there are two bits available per

sample for transmitting additional information over the

JESD204B link. The options are tail bits or control bits. By

default, tail bits of 0b00 value are used.

•

Tail bits are dummy bits sent over the link to complete the

two octets and do not convey any information about the input

signal. Tail bits can be fixed zeros (default) or pseudo-

random numbers (Address 0x5F, Bit 6).

•

One or two control bits can be used instead of the tail bits

through Address 0x72, Bits[7:6]. The tail bits can be set

using Address 0x14, Bits[7:5], and the tail bits can be

enabled using Address 0x5F, Bit 6.

Set lane identification values.

•

JESD204B allows parameters to identify the device and lane.

These parameters are transmitted during the ILAS phase, and

they are accessible in the internal registers.

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