AD9683 datasheet(37/45 Pages) AD

37 / 45 page

AD9683

Data Sheet

Rev. D | Page 36 of 44

Reg

Addr

(Hex)

Reg Addr

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x14

Output mode

JESD204B CS bits assignment

(in conjunction with Address 0x72):

000 = {overrange||underrange, valid},

001 = {overrange, underrange},

010 = {overrange||underrange, blank},

011 = {blank, valid},

100 = {blank, blank},

101 = {underrange, overrange},

110 = {valid, overange||underrange},

111 = {valid, blank}

ADC

output

disable

ADC data

invert:

0 = normal

(default),

1 =

inverted

Data format select (DFS) :

00 = offset binary,

01 = twos complement

0x01

0x15

CML output

adjust

JESD204B CML differential output drive

level adjustment:

000 = 75% of nominal ( 438 mV p-p),

001 = 83% of nominal (488 mV p-p),

010 = 91% of nominal (538 mV p-p),

011 = nominal (default) (588 mV p-p),

100 = 109% of nominal (638 mV p-p),

101 = 117% of nominal (690 mV p-p),

110 = 126% of nominal (740 mV p-p),

111 = 134% of nominal (790 mV p-p)

0x03

0x18

Input span

select

Main reference full-scale VREF adjustment:

0 1111 = internal 2.087 V p-p,

…

0 0001 = internal 1.772 V p-p,

0 0000 = internal 1.75 V p-p (default),

1 1111 = internal 1.727 V p-p,

…

1 0000 = internal 1.383 V p-p

0x00

0x19

User Test

Pattern 1 LSB

User Test Pattern 1 LSB; use in conjunction with Address 0x0D and Address 0x61

0x1A

User Test

Pattern 1 MSB

User Test Pattern 1 MSB

0x1B

User Test

Pattern 2 LSB

User Test Pattern 2 LSB

0x1C

User Test

Pattern 2 MSB

User Test Pattern 2 MSB

0x1D

User Test

Pattern 3 LSB

User Test Pattern 3 LSB

0x1E

User Test

Pattern 3 MSB

User Test Pattern 3 MSB

0x1F

User Test

Pattern 4 LSB

User Test Pattern 4 LSB

0x20

User Test

Pattern 4 MSB

User Test Pattern 4 MSB

0x21

PLL low encode

00 = for lane speeds of

>2 Gbps,

01 = for lane speeds of

<2 Gbps

0x00

0x3A

SYNCINB±/

SYSREF±

control

JESD204B

realign

SYNCINB±:

0 = normal

mode,

1 = realigns

lane on

every

active

SYNCINB±

JESD204B

realign

SYSREF±:

0 =

normal

mode,

1 =

realigns

lane on

every

active

SYSREF±

mode:

0 =

continuous

reset clock

dividers,

1 = sync

on next

SYSREF±

rising edge

only

SYSREF±

enable:

0 =

disabled,

1 =

enabled.

Note that

this bit

self-clears

after

SYSREF if

SYSREF±

mode = 1

Enable

internal

SYSREF±

buffer;

0 = buffer

disabled,

external

SYSREF±

ignored;

1 = buffer

enabled,

use

external

SYSREF±

0x00

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