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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC933FDH датащи(PDF) 37 Page - NXP Semiconductors |
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P89LPC933FDH датащи(HTML) 37 Page - NXP Semiconductors |
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37 / 75 page  9397 750 15113 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 06 — 20 June 2005 37 of 75 Philips Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 8.19.7 Alternating output mode In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle. 8.19.8 PLL operation The PWM module features a PLL that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1. (1) Where: N is the value of PLLDV.3 to PLLDV.0. Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK ⁄ 16. Fig 12. Alternate output mode TIMER VALUE 002aaa895 0 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) PWM OUTPUT A (or C) (P2.6) PWM OUTPUT B (or D) (P1.6) PLL frequency PCLK N1 + () ------------------ = |
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