P89LPC933FDH datasheet(52/75 Pages) PHILIPS

52 / 75 page

9397 750 15113

Product data sheet

Rev. 06 — 20 June 2005

52 of 75

Philips Semiconductors

P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.28.10 Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the

P89LPC933/934/935/936 User manual for speciﬁc

information). This has the same effect as having a non-zero status byte. This allows an

application to be built that will normally execute user code but can be manually forced into

ISP operation. If the factory default setting for the boot vector is changed, it will no longer

point to the factory preprogrammed ISP boot loader code. After programming the ﬂash,

the status byte should be programmed to zero in order to allow execution of the user’s

application code beginning at address 0000H.

8.29 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC933/934/935/936 must be deﬁned at

power-up and therefore cannot be set by the program after start of execution. These

features are conﬁgured through the use of the ﬂash byte UCFG1. Please see the

P89LPC933/934/935/936 User manual for additional details.

8.30 User sector security bytes

There are eight User Sector Security Bytes on the P89LPC933/934/935/936 device. Each

byte corresponds to one sector. Please see the

P89LPC933/934/935/936 User manual for

additional details.

A/D converter

9.1 General description

The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximation

analog-to-digital converter modules sharing common control logic. The P89LPC933/934

have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additional

DAC module. A block diagram of the A/D converter is shown in Figure 23. Each A/D

consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input

signal to one of two comparator inputs. The control logic in combination with the SAR

drives a digital-to-analog converter which provides the other input to the comparator. The

output of the comparator is fed to the SAR.

9.2 Features

s Two (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation

A/D converters with common control logic (one A/D on the P89LPC933/934).

s Four result registers for each A/D.

s Six operating modes:

x Fixed channel, single conversion mode.

x Fixed channel, continuous conversion mode.

x Auto scan, single conversion mode.

x Auto scan, continuous conversion mode.

x Dual channel, continuous conversion mode.

x Single step mode.

s Four conversion start modes:

x Timer triggered start.

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