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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC933FDH датащи(PDF) 59 Page - NXP Semiconductors |
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P89LPC933FDH датащи(HTML) 59 Page - NXP Semiconductors |
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59 / 75 page  9397 750 15113 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 06 — 20 June 2005 59 of 75 Philips Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 12. Dynamic characteristics Table 12: Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial, unless otherwise specified. [1] [2] Symbol Parameter Conditions Variable clock fosc =12MHz Unit Min Max Min Max fOSC(RC) internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz fOSC(WD) internal watchdog oscillator frequency 320 520 320 520 kHz fosc oscillator frequency 0 12 - - MHz Tcy(CLK) clock cycle time see Figure 27 83 - - - ns fCLKLP low power select clock frequency 0 8 - - MHz Glitch filter tgr glitch rejection P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns tsa signal acceptance P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock tCHCX clock HIGH time see Figure 27 33 Tcy(CLK) − tCLCX 33 - ns tCLCX clock LOW time see Figure 27 33 Tcy(CLK) − tCHCX 33 - ns tCLCH clock rise time see Figure 27 -8 - 8 ns tCHCL clock fall time see Figure 27 -8 - 8 ns Shift register (UART mode 0) tXLXL serial port clock cycle time see Figure 25 16Tcy(CLK) - 1333 - ns tQVXH output data setup to clock rising edge time see Figure 25 13Tcy(CLK) - 1083 - ns tXHQX output data hold after clock rising edge time see Figure 25 -Tcy(CLK) + 20 - 103 ns tXHDX input data hold after clock rising edge time see Figure 25 -0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 25 150 - 150 - ns SPI interface fSPI SPI operating frequency slave 0 CCLK ⁄6 0 2.0 MHz master - CCLK ⁄4 - 3.0 MHz tSPICYC SPI cycle time see Figure 26, 28, 29, 30 slave 6 ⁄ CCLK - 500 - ns master 4 ⁄ CCLK - 333 - ns tSPILEAD SPI enable lead time (slave) see Figure 29, 30 250 - 250 - ns tSPILAG SPI enable lag time (slave) see Figure 29, 30 250 - 250 - ns |
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