P89LPC933FDH datasheet(33/75 Pages) PHILIPS

33 / 75 page

9397 750 15113

Product data sheet

Rev. 06 — 20 June 2005

33 of 75

Philips Semiconductors

P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

8.16 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,

P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin will

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this input will function either as an external reset input or as a digital input

as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection

deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1).

• Power-on detect.

• Brownout detect.

• Watchdog timer.

• Software reset.

• UART break character detect reset.

For every reset source, there is a ﬂag in the reset register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a logic 0 to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

8.16.1 Reset vector

Following reset, the P89LPC933/934/935/936 will fetch instructions from either address

0000H or the boot address. The boot address is formed by using the boot vector as the

high byte of the address and the low byte of the address = 00H.

The boot address will be used if a UART break reset occurs, or the non-volatile boot

status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC933/934/935/936 User manual). Otherwise, instructions will be fetched from

address 0000H.

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