 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
AD9656EBZ датащи(PDF) 29 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9656EBZ датащи(HTML) 29 Page - Analog Devices |
|
|
29 / 47 page  AD9656 Data Sheet Rev. A | Page 28 of 46 Resynchronization Figure 66 depicts the resynchronization timing for the AD9656 JESD204B interface. When the subclass 1 receiving logic device is ready to resynchronize, it asserts the SYNCINB signal and issues a SYSREF request. Note that once SYSREF is applied, the JESD204B internal clocks are reset and take up to 2 LMFC periods to fully settle. Once the new phase of LMFC is stable, SYNCINB must remain asserted for at least four LMFC cycles for the AD9656 to respond by sending the K28.5 characters. This commences the CGS portion of subclass 1 synchronization. Once the Tx deasserts the SYNCINB signal, the ILAS starts on the second LMFC boundary. SYSREF REQUEST (ASSERT SYNCINB) START OF SYSREF START CGS SYNCINB DEASSERT SYSREF SYNCINB DATA OUT LMFCADC < 2 LMFCs FOR STABLE LMFC AFTER SYSREF UP TO 6 LMFCs AFTER SYREF RISING EDGE TO START CGS ILAS START ON SECOND LMFC AFTER SYNCINB DEASSERT ADC DATA K28.5 ILAS Figure 66. JESD204B Tx Resynchronization Timing |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
