AD9656EBZ datasheet(43/47 Pages) AD

43 / 47 page

AD9656

Data Sheet

Rev. A | Page 42 of 46

Addr

(Hex)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Notes/

Comments

0x109

Clock divider

sync control

Clock

divider

sync

mode:

0 = use

SYNC pin,

1 = use

SYSREF±

pins

Reserved

Reset

clock

divider

sync

received

Sync clock

divider

enable:

0 =

disabled,

1 =

enabled

0x80

0x10A

Clock divider

sync received

Open

Clock

divider

sync

received

0x00

Read only.

MEMORY MAP REGISTER DESCRIPTIONS

For additional general information about functions controlled

in Register 0x00 to Register 0xFF, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

Device Index (Register 0x05)

Certain features in the map that are designated as local can be set

independently for each channel, whereas other features apply

globally to all channels (depending on context), regardless of

the channel is selected. Bits[3:0] of Register 0x05 can select

which data channels are affected.

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment

they are written. Setting Bit 0 of the transfer register high

invokes the settings in the resolution/sample rate override

Power Modes (Register 0x08)

Bit 5—PDWN Pin Function

If set to 1, the PDWN pin initiates standby mode. If set to 0

(cleared), the PDWN pin initiates full power-down mode.

Bit 4—JTX Standby Mode

If set, the JTX block enters standby mode when chip standby is

activated. Only the PLL is left running in standby mode. If

cleared, the JTX block remains running when chip standby is

activated.

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), all ADC channels and the

JTX block are active.

In full power-down mode (Bits[1:0] = 01), all ADC channels and

the JTX block are powered down, and the digital datapath clocks

are disabled, while the digital datapath is reset. The outputs are

disabled.

In standby mode (Bits[1:0] = 10), all ADC channels are partially

powered down, and the digital datapath clocks are disabled. If

JTX standby mode is set, the outputs are also disabled.

During a digital reset (Bits[1:0] = 11), all the digital datapath clocks

and the outputs (where applicable) on the chip are reset, except

for the SPI port.

Note that the SPI is always left under control of the user; that is,

it is never automatically disabled or in reset (except by power-

on reset). When the digital reset is deactivated, a foreground

calibration sequence is initiated.

Enhancement Control (Register 0x0C)

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct conversion

receivers, chopping in the first stage of the AD9656 is a feature

that can be enabled by setting Bit 2. In the frequency domain,

chopping translates offsets and other low frequency noise to

fCLK/2 where it can be filtered.

Output Mode (Register 0x14)

Bits[7:5]—JTX CS Mode

Defines the meaning of the JTX control bits.

Bits[1:0]—Output Format

By default, this field is set to 1 for data output in twos

complement format. Setting this field to 0 changes the output

mode to offset binary.

Clock Phase Control (Register 0x16)

Bits[6:4]—Input Clock Phase Adjust

When the clock divider (Register 0x0B) is used, the applied

clock is at a higher frequency than the internal sampling clock.

Bits[6:4] determine at which phase the external clock sampling

occurs. This is only applicable when the clock divider is used.

Setting Bits[6:4] greater than Register 0x0B, Bits[2:0] is prohibited.

Table 20. Input Clock Phase Adjust Options

Input Clock Phase Adjust, Bits[6:4]

Number of Input Clock

Cycles of Phase Delay

000 (default)

001

010

011

100

101

110

111

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