Data Sheet

AD9656

Rev. A | Page 39 of 46

Addr

(Hex)

Register Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Notes/

Comments

0x14

Output mode

JTX CS mode:

000 = {overrange || underrange, valid flag},

001 = {overrange, underrange},

010 = {overrange || underrange, blank},

011 = {blank, valid flag},

100 = {blank, blank},

Others = {overrange || underrange,

valid flag}

ADC

output

disable:

0 =

enabled,

1 =

disabled

(local)

Open

Open

Output format:

00 = offset binary,

01 = twos

complement

0x01

Bits[7:5]

are not

applicable

when using

the default

16-bit

resolution.

0x15

Output adjust

Open

Open

Open

Open

Open

Typical CML differential output drive level:

000 = 473 mV p-p,

001 = 524 mV p-p,

010 = 574 mV p-p,

011 = 621 mV p-p (default),

100 = 667 mV p-p,

101 = 716 mV p-p,

110 = 763 mV p-p,

111 = 811 mV p-p

0x03

0x16

Clock phase

control

Open

Input clock phase adjust[2:0]

(value is number of input clock cycles of

phase delay)

Open

Open

Open

Open

0x00

0x18

Input span

select

Internal VREF

adjustment[1:0]:

00 = 1.0 V,

01 = 1.2 V,

10 = 1.3 V,

11 = 1.4 V

Open

Open

Open

Differential span adjustment:

000 = 50% of normal,

001 = 57% of normal,

010 = 67% of normal,

011 = 80% of normal,

100 = normal

0x04

0x19

User Test

Pattern 1 LSB

User Test Pattern 1[7:0]

0x00

0x1A

User Test

Pattern 1 MSB

User Test Pattern 1[15:8]

0x00

0x1B

User Test

Pattern 2 LSB

User Test Pattern 2[7:0]

0x00

0x1C

User Test

Pattern 2 MSB

User Test Pattern 2[15:8]

0x00

0x21

FLEX_SERIAL_

CONTROL

Open

Open

Open

Open

PLL low

rate

mode:

0 = lane

rate ≥

2 Gbps

1 = lane

rate <

2 Gbps

Open

Open

Open

0x00

0x22

FLEX_SERIAL_

CH_STAT

Open

Open

Open

Open

Open

Open

Open

Channel

power-

down

(local)

0x00

0x3A

SYSREF_CTRL

Open

Open

Open

0 = normal

mode,

1 = realign

the lanes

on every

active

SYNCINB±

0 =

realign

the lanes

only

when

SYSREF±

causes a

resync

of the

counters,

1 =

realign

the lanes

on every

SYSREF±

Open

Open

Open

0x00

0x3B

REALIGN_

PATTERN_CTRL

This pattern is written into the FIFO when a lane is being aligned:

00 = lane outputs constant zero, 55 = lane outputs toggling pattern

0x55

0x5E

JESD204B

quick

configuration

0x41 = four converters, one lane; 0x42 = four converters, two lanes; 0x44 = four converters, four lanes; 0x22 = two converters,

two lanes; 0x21 = two converters, one lane; 0x11 = one converter, one lane

0x00

Self

clearing,

always

reads

0x00.