AD9656EBZ datasheet(27/47 Pages) AD

27 / 47 page

AD9656

Data Sheet

Rev. A | Page 26 of 46

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 63 and Figure 64, the power dissipated by

the AD9656 is proportional to the sample rate.

The AD9656 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In power-down mode,

the ADC typically dissipates 14 mW. During power-down, the

output drivers are placed in a high impedance state. When the

PDWN pin is asserted low, the AD9656 returns to normal operating

mode. Note that PDWN is referenced to SVDD and must not

exceed that supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and must then be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode; shorter power-down cycles

result in proportionally shorter wake-up times. When using the

SPI port interface, the user can place the ADC in power-down

mode or standby mode. Standby mode allows the user to keep

the internal reference circuitry powered when faster wake-up

times are required. See the Memory Map section for more

information about using these features.

0.30

0.40

0.45

0.35

0.50

0.55

0.60

0.65

0.70

0.75

0.80

100

120

SAMPLE RATE (MSPS)

80MSPS

SETTING

65MSPS

SETTING

50MSPS

SETTING

125MSPS

SETTING

105MSPS

SETTING

Figure 63. Total Power vs. fSAMPLE for fIN = 9.7 MHz, Four Channels (VREF = 1.4 V)

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

100

120

SAMPLE RATE (MSPS)

125MSPS

SETTING

80MSPS

SETTING

65MSPS

SETTING

50MSPS

SETTING

105MSPS

SETTING

Figure 64. Total Power vs. fSAMPLE for fIN = 9.7 MHz, Four Channels (VREF = 1.0 V)

DIGITAL OUTPUTS

JESD204B Transmit Top Level Description

The AD9656 digital output uses the JEDEC Standard No.

JESD204B, Serial Interface for Data Converters. JESD204B is a

protocol to link the AD9656 to a digital processing device over a

serial interface with link speeds up to 8.0 Gbps. The benefits of

the JESD204B interface include a reduction in the required

board area for data interface routing and the enabling of smaller

packages for converter and logic devices. The AD9656 supports

single, dual, and four lane interfaces.

JESD204B Overview

The JESD204B data transmit block, JTX, assembles the parallel

data from the ADC into frames and uses 8b/10b encoding, as well

as optional scrambling, to form serial output data. Lane

synchronization is supported using special characters during the

initial establishment of the link, and additional synchronization is

embedded in the data stream thereafter. A matching external

receiver is required to lock onto the serial data stream and recover

the data and clock. For additional information about the

JESD204B interface, refer to the JESD204B standard.

The AD9656 JESD204B transmit block maps the output of the

four ADCs over a link. A link can be configured to use either

single, dual, or four serial differential outputs, which are called

lanes. The JESD204B specification refers to a number of parameters

to define the link, and these parameters must match between the

JESD204B transmitter (AD9656 output) and receiver.

The JESD204B link is described according to the following

parameters:

•

S = samples transmitted/single converter/frame cycle

(AD9656 value = 1)

•

M = number of converters/converter device (AD9656

value = 4)

•

L = number of lanes/converter device (AD9656 value =

1, 2, or 4)

•

N = converter resolution (AD9656 value = 16)

•

N’ = total number of bits per sample (AD9656 value = 16)

•

CF = number of control words/frame clock cycle/converter

device (AD9656 value = 0)

•

CS = number of control bits/conversion sample (AD9656

value = 0)

•

K = number of frames per multiframe (configurable on

the AD9656)

•

HD = high density mode (AD9656 value = 0)

•

F = octets/frame (AD9656 value = 2, 4, or 8, dependent

upon L = 4, 2, or 1)

•

C = control bit (overrange, overflow, underflow;

unavailable in the AD9656 default mode)

•

T = tail bit (unavailable in the AD9656 default mode)

•

SCR = scrambler enable/disable (configurable on the AD9656)

•

FCHK = checksum for the JESD204B parameters

(automatically calculated and stored in the register map)

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