AD9656EBZ datasheet(26/47 Pages) AD

26 / 47 page

Data Sheet

AD9656

Rev. A | Page 25 of 46

Another option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 60. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

0Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

Figure 60. Differential LVDS Sample Clock (Up to 1 GHz)

In some applications, it is acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 µF capacitor (see

Figure 61).

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 61. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9656 contains an input clock divider with the ability to

divide the input clock by integer values from 1 to 8.

The AD9656 clock divider can be synchronized using the

external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the

clock divider to resynchronize on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to the initial state. This synch-

ronization feature allows multiple devices to have the clock

dividers aligned to guarantee simultaneous input sampling.

Alternatively, SYSREF± can reset the clock divider by setting

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety

of internal timing signals and, as a result, can be sensitive to the

clock duty cycle. Commonly, a ±5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9656 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This feature minimizes

performance degradation in cases where the clock input duty

cycle deviates more than the specified ±5% from the nominal 50%

duty cycle. Enabling the DCS function can significantly improve

noise and distortion performance for clock input duty cycles

ranging from 30% to 45% and from 55% to 70%.

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The loop has

a time constant associated with it that must be considered in

applications in which the clock rate can change dynamically. A

wait time of 1.5 µs to 5 µs is required after a dynamic clock

frequency increase or decrease before the DCS loop is relocked

to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 log10













A t

2π

In this equation, the rms aperture jitter represents the root sum

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. Intermediate

frequency (IF) under-sampling applications are particularly

sensitive to jitter (see Figure 62).

Treat the clock input as an analog signal in cases where aperture

jitter can affect the dynamic range of the AD9656. Separate power

supplies for clock drivers from the supplies for the ADC output

driver to avoid modulating the clock signal with digital noise.

Low jitter, crystal controlled oscillators make the best clock

sources. If the clock is generated from another type of source

(by gating, dividing, or other methods), retime it by the original

clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in depth information about jitter

performance as it relates to ADCs.

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 62. Ideal SNR vs. Analog Input Frequency and Jitter

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