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AD9656EBZ датащи(PDF) 42 Page - Analog Devices

номер детали AD9656EBZ
подробное описание детали  Quad, 16-Bit, 125 MSPS 1.8 V Analog-to-Digital Converter
PDF  47 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9656EBZ датащи(HTML) 42 Page - Analog Devices

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Data Sheet
AD9656
Rev. A | Page 41 of 46
Addr
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
Notes/
Comments
0x79
JESD204B
CHKSUM1
JESD204B serial checksum value in link configuration, see Table 12 for Lane 1 (FCHK)
Read only.
0x7A
JESD204B
CHKSUM2
JESD204B serial checksum value in link configuration, see Table 12 for Lane 2 (FCHK)
Read only.
0x7B
JESD204B
CHKSUM3
JESD204B serial checksum value in link configuration, see Table 12 for Lane 3 (FCHK)
Read only.
0x80
JTX physical
lane disable
Open
Open
Open
Open
Lane 3:
0 =
enabled,
1 =
disabled
Lane 2:
0 = enabled,
1 = disabled
Lane 1:
0 =
enabled,
1 =
disabled
Lane 0:
0 =
enabled,
1 =
disabled
0x00
Lane
serialize
and
output
driver
powered
down.
0x82
JESD204B Lane
Assign 1
Open
Physical Lane 1 assignment:
000 = Logical Lane 0,
001 = Logical Lane 1,
010 = Logical Lane 2,
011 = Logical Lane 3
Open
Physical Lane 0 assignment:
000 = Logical Lane 0,
001 = Logical Lane 1,
010 = Logical Lane 2,
011 = Logical Lane 3
0x10
0x83
JESD204B Lane
Assign 2
Open
Physical Lane 3 assignment:
000 = Logical Lane 0,
001 = Logical Lane 1,
010 = Logical Lane 2,
011 = Logical Lane 3
Open
Physical Lane 2 assignment:
000 = Logical Lane 0,
001 = Logical Lane 1,
010 = Logical Lane 2,
011 = Logical Lane 3
0x32
0x86
JESD204B lane
inversion
Open
Open
Open
Open
Lane 3:
0 = no
invert,
1 = invert
Lane 2:
0 = no invert,
1 = invert
Lane 1:
0 = no
invert,
1 = invert
Lane 0:
0 = no
invert,
1 = invert
0x00
0x8B
JESD204B
LMFC offset
Open
Open
Open
Local multiframe clock (LMFC) phase offset value; reset value for LMFC phase
counter when SYSREF± is asserted; used for deterministic delay applications
0x00
0xA0
JTX User
Pattern
Octet 0, LSB
User test pattern least significant byte, Octet 0
0x00
0xA1
JTX User
Pattern
Octet 0, MSB
User test pattern most significant byte, Octet 0
0x00
0xA2
JTX User
Pattern
Octet 1, LSB
User test pattern least significant byte, Octet 1
0x00
0xA3
JTX User
Pattern
Octet 1, MSB
User test pattern most significant byte, Octet 1
0x00
0xA4
JTX User
Pattern
Octet 2, LSB
User test pattern least significant byte, Octet 2
0x00
0xA5
JTX User
Pattern
Octet 2, MSB
User test pattern most significant byte, Octet 2
0x00
0xA6
JTX User
Pattern
Octet 3, LSB
User test pattern least significant byte, Octet 3
0x00
0xA7
JTX User
Pattern
Octet 3, MSB
User test pattern most significant byte, Octet 3
0x00
0xF5
JTX converter
mapping
JTX Converter 3:
0 = ADCA,
1 = ADCB,
2 = ADCC,
3 = ADCD
JTX Converter 2:
0 = ADCA,
1 = ADCB,
2 = ADCC,
3 = ADCD
JTX Converter 1:
0 = ADCA,
1 = ADCB,
2 = ADCC,
3 = ADCD
JTX Converter 0:
0 = ADCA,
1 = ADCB,
2 = ADCC,
3 = ADCD
0xE4
0x100
Resolution/
sample rate
override
Open
Override
enable
Resolution:
0 = 16 bits,
1 = 14 bits,
2 = 12 bits,
3 = 10 bits
Open
Sample rate:
001 = 40 MSPS,
010 = 50 MSPS,
011 = 65 MSPS,
100 = 80 MSPS,
101 = 105 MSPS,
110 = 125 MSPS
0x00
Sample
rate
override
(requires
transfer
register,
0xFF).
0x101
User I/O
Control 2
Open
Open
Open
Open
Open
Open
Open
SDIO
pull-down
0x00
Disables
SDIO
pull-down.
0x102
User I/O
Control 3
Open
Open
Open
Open
VCM
power-
down
Open
Open
Open
0x00
VCM
control.



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