AD9656EBZ datasheet(36/47 Pages) AD

36 / 47 page

Data Sheet

AD9656

Rev. A | Page 35 of 46

SERIAL PORT INTERFACE (SPI)

The AD9656 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that can

be further divided into fields. These fields are documented in the

Memory Map section. For general operational information, see

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 17). The SCLK pin synchronizes

the read and write data presented from/to the ADC. The SDIO pin

is a dual purpose pin that allows data to be sent and read from

the internal ADC memory map registers. The CSB pin is an active

low control that enables or disables the read and write cycles.

Table 17. Serial Port Interface Pins

Function

SCLK

Serial Clock. The serial shift clock input, which

synchronizes serial interface reads and writes.

SDIO

Serial Data Input/Output. A dual purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

CSB

Chip Select Bar. An active low control that gates the read

and write cycles.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example and

definition of the serial timing can be found in Figure 74 and

Table 7.

Other modes involving the CSB pin are available. The CSB pin

can be held low indefinitely, which permanently enables the

device; this is called streaming. The CSB pin can stall high

between bytes to allow for additional external timing. When

CSB is tied high, SPI functions are placed in a high impedance

mode. This mode turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase and the length is determined

by the W0 and W1 bits.

All data is composed of 8-bit words. The first bit of each individual

byte of serial data indicates whether a read or write command is

issued. This allows the SDIO pin to change direction from an

input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory.

If the instruction is a readback operation, performing a readback

causes the SDIO pin to change direction from an input to an

output at the appropriate point in the serial frame.

Input data is registered on the rising edge of SCLK and output data

is transmitted on the falling edge. After the address information

passes to the converter that is requesting a read, the SDIO line

transitions from an input to an output within one-half of a clock

cycle. This timing ensures that when the falling edge of the next

clock cycle occurs, data can be safely placed on this serial line

for the controller to read.

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Table 17 make up the physical interface

between the user programming device and the serial port of the

AD9656. The SCLK pin and the CSB pin function as inputs when

using the SPI interface. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during readback.

The AD9656 has a separate supply pin for the SPI interface,

SVDD. The SVDD pin can be set to any level between 1.8 V

and 3.3 V to enable operation with a SPI bus at these voltages

without requiring level translation. If the SPI port is not used,

SVDD can be tied to the DRVDD voltage.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note,

Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

When the full dynamic performance of the converter is required,

do not activate the SPI port. Because the SCLK signal, the CSB

signal, and the SDIO signal are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices, it

may be necessary to provide buffers between this bus and the

AD9656 to prevent these signals from transitioning at the

converter inputs during critical sampling periods.

SPI ACCESSIBLE FEATURES

Table 18 provides a brief description of the features that are

accessible via the SPI. These features are described in general in

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9656 device-specific features are described in

the Memory Map Register Descriptions section. Information in

the AD9656 data sheet takes precedence over information in

AN-877 Application Note, where it relates to the AD9656.

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