AD9656EBZ datasheet(38/47 Pages) AD

38 / 47 page

Data Sheet

AD9656

Rev. A | Page 37 of 46

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

channel index and transfer registers (Address 0x05 and

Address 0xFF); and the ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x10A).

The memory map register table (see Table 19) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x14,

the output mode register, has a hexadecimal default value of

0x01. This means that Bit 0 = 1 and the remaining bits are 0s.

This setting is the default output format value, which is twos

complement. For general information on this function and

others, see the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI. See Table 19 for SPI register information

specific to the AD9656.

Open and Reserved Locations

All address and bit locations that are not included in Table 19

are not supported for this device. Write 0s to unused bits of a

valid address location. Writing to these locations is required

only when part of an address location is open (for example,

Address 0x18). If the entire address location is open (for example,

Address 0x13), do not write to this address location.

Default Values

After the AD9656 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table (see Table 19).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel Specific Registers

Some channel setup functions can be programmed to a different

value for each channel. In these cases, channel address locations

are internally duplicated for each channel. These registers and bits

are designated in Table 19 as local. These local registers and bits

can be accessed by setting the appropriate Channel 0, Channel 1,

Channel 2, or Channel 3 bit in Register 0x05. If four bits are set,

the subsequent write affects the registers of all four channels. In a

read cycle, set only one of the channels to read one of the four

registers. If all bits are set during an SPI read cycle, the device

returns the value for Channel 0. Registers and bits designated as

global in Table 19 affect the entire device and the channel features

for which independent settings are not allowed between channels.

The settings in Register 0x05 do not affect the global registers

and bits.

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