IC-HTP datasheet(20/51 Pages) ICHAUS

20 / 51 page

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iC-HTP

DUAL CW P-TYPE LASER DIODE DRIVER

Rev B1, Page 20/51

COMP2

Addr. 0x18; bit 6:4

R/W 011

000

Minimum compensation current for the channel 2

regulator, slower response

. . .

111

Maximum compensation current for the channel 2

regulator, faster response

Table 36: Current compensation channel 2

Alternatively it is possible to use external capacitors

connected to pins CIx and CIHx. In this case, register

bit ECIEx should be set to 1 and COMPx to its highest

value, "111".

ECIE1

Addr. 0x10; bit 1

R/W 0

External CI capacitor for channel 1 disconnected

External CI capacitor for channel 1 connected

Table 37: Enable external CI capacitor channel 1

ECIE2

Addr. 0x15; bit 1

R/W 0

External CI capacitor for channel 2 disconnected

External CI capacitor for channel 2 connected

Table 38: Enable external CI capacitor channel 2

The regulator is offset compensated in order to pre-

vent optical power drifts. Offset compensation can be

disabled by setting register bit EOCx to 0.

EOC1

Addr. 0x10; bit 4

R/W 1

Channel 1 regulator offset compensation disabled

Channel 1 regulator offset compensation enabled

Table 39: Enable offset compensation channel 1

EOC2

Addr. 0x15; bit 4

R/W 1

Channel 2 regulator offset compensation disabled

Channel 2 regulator offset compensation enabled

Table 40: Enable offset compensation channel 2

An internal oscillator is used for the offset compensa-

tion. A watchdog timer (WDT) is included in order to

monitor proper function of the oscillator. If an error is

detected by the WDT, the laser channels are operated

with an offset to ensure a safe power level, OSCERR

error bit is set in STATUS0 register and the error event

is signaled at pin NCHK. This error signaling can be

suppressed using the mask register bit MOSCERR (set

to 1).

MOSCERR

Addr. 0x1D; bit 0

R/W 0

Oscillator error (watchdog) will be signaled at NCHK

Oscillator error (watchdog) will not be signaled at

NCHK

Table 41: Oscillator watchdog error mask

iC-HTP monitors the saturation voltage of the regula-

tor´s output transistor at pin LDAx. The LDA saturation

threshold can be configured through register bits RL-

DASx.

RLDAS1

Addr. 0x13; bit 3:2

R/W 00

V(LDA1) > VBL1-0.5 V sets the LDASAT1 alarm bit

V(LDA1) > VBL1-0.8 V sets the LDASAT1 alarm bit

V(LDA1) > VBL1-1.0 V sets the LDASAT1 alarm bit

V(LDA1) > VBL1-1.2 V sets the LDASAT1 alarm bit

Table 42: LDA saturation threshold selection

channel 1

RLDAS2

Addr. 0x18; bit 3:2

R/W 00

V(LDA2) > VBL2-0.5 V sets the LDASAT2 alarm bit

V(LDA2) > VBL2-0.8 V sets the LDASAT2 alarm bit

V(LDA2) > VBL2-1.0 V sets the LDASAT2 alarm bit

V(LDA2) > VBL2-1.2 V sets the LDASAT2 alarm bit

Table 43: LDA saturation threshold selection

channel 2

If the LDAx voltage goes upper than the LDA saturation

threshold the LDASATx error bit in STATUS1 register

will be set and it will be signaled through output pin

NCHK. Setting the mask register bit MLDASATx to 1

suppresses the signaling at NCHK.

MLDASAT1

Addr. 0x1D; bit 2

R/W 1

LDASAT1 event will be signaled at NCHK

LDASAT1 event will not be signaled at NCHK

Table 44: LDA saturation error mask channel 1

MLDASAT2

Addr. 0x1D; bit 3

R/W 1

LDASAT2 event will be signaled at NCHK

LDASAT2 event will not be signaled at NCHK

Table 45: LDA saturation error mask channel 2

Laser channel enabling and error handling

With pin INS/WKR or EMC unconnected, a correspond-

ing error signal will be generated (INSOPEN, EM-

COPEN). Any of these error signals will disable the

laser channels.

Setting DISC1 and DISC2 to 1(default) disables the

corresponding channel.

The errors in STATUS0 and STATUS1 registers disable

the laser channels. Every change in the STATUS regis-

ters is signaled at pin NCHK, unless the error event is

masked by the corresponding error mask bit.

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