IC-GD datasheet(39/55 Pages) ICHAUS

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iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 39/55

OPCODES

The first byte sent via SPI contains the address of the

iC and the command. The address is defined by three

bits that address the iC when they match its hard-wired

address. A broadcast is also possible; here all chips are

addressed and the address is ignored; the command

defines the type of access. Possible are:

• PROCESS DATA x: The data of the primary chan-

nel is transmitted. The iC accepts the data when the

addressed channel is configured as input. The iC out-

puts data when the addressed channel is configured

as output. The bit width is adjusted automatically for

the chosen mode.

• READ CH_STAT_REG: The channel status register

is read, output and reset (RD + RST).

• READ IRQ_FLAG_REG: The interrupt-flag register

is read and output. This way, the cause for an in-

terrupt can be determined. It can be reset when no

interrupt is indicated any more (formed combinato-

rial).

• SYNC: The current value is sampled and stored for

channels that are configured as input (analog input,

digital input, counter, temperature measurement). For

channels that are configured as output, the last writ-

ten value is output. The used edge can be config-

ured per channel via the bit SYNC_INV_x. The Op-

code SYNC 1&2 – rising/falling edge can reproduce

a rising or falling edge and triggers synchronization

only when the edge matches the configuration via

SYNC_INV_x. The SYNC command has no effect

if the channel does not operate synchronously (se-

lectable via SYNC_SEL_x).

• READ INTERNAL REGISTER (single): The ad-

dressed register is output.

• WRITE INTERNAL REGISTER (single): The ad-

dressed register is written by the following byte.

• READ INTERNAL REGISTER (continuous): Oper-

ates like single; here the address is incremented au-

tomatically after each byte. This enables reading

various consecutive registers. Usage in broadcast is

not possible.

• WRITE INTERNAL REGISTER (continuous): Op-

erates like single; here the address is incremented

automatically after each byte. This enables the writ-

ing of consecutive register. Usage in broadcast is

possible. All iCs accept the same data.

• I2C TRANSFER/STATUS: The I2C TRANSFER com-

mand allows addressing components connected to

the iC via I2C. The iC operates as bridge. Therefore

the regular commands of I2C are mapped. Details

can be found in chapter I2C. Communication runs in

the background. Via I2C STATUS can be polled for

its completion.

Opcodes

Bits Description Values

2:0

Address

0...7: Up to 8 chips individually addressable

Broadcast

0 = single

1 = broadcast (address irrelevant)

7:4

Command

0000 = PROCESS DATA 1P

0001 = PROCESS DATA 2P

0010 = PROCESS DATA 1P & 2P

0011 = READ CH_STAT_REG

0100 = READ IRQ_FLAG_REG

0101 = SYNC 1

0110 = SYNC 2

0111 = SYNC 1&2

1000 = SYNC 1&2 – rising edge

1001 = SYNC 1&2 – falling edge

1010 = READ INTERNAL REGISTER (single)

1011 = WRITE INTERNAL REGISTER (single)

1100 = READ INTERNAL REGISTER (continous) (*)

1101 = WRITE INTERNAL REGISTER (continous)

1110 = I2C TRANSFER

1111 = I2C STATUS

Table 23: Opcodes

(*) Not to be used in broadcast

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