IC-GD datasheet(34/55 Pages) ICHAUS

34 / 55 page

prel

imin

ary

prel

imin

ary

iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 34/55

COUNTER

Via the two digital inputs with their following spike filters,

two 32-bit wide counters can be operated. In single

mode, the counters are operated independently. In

dual mode (see below), one counter is controlled by

both inputs. The counters can also be used as PWM

generators.

For each counter, one reference value can be config-

ured that sets a status bit and causes an interrupt, when

reached. In addition, a bit can be configured that de-

termines whether an interrupt is caused once or every

time the reference value is reached. In the latter case it

can be reset via the register SPI_LOCK_RESET. This

prevents the setting of a status bit and the triggering of

an interrupt in case the counter fluctuates around the

reference value or is at the reference value. The same

functions are available for the second reference value

and the overflow and underflow of the counter.

The bit CNT_RAR allows the configuration of a counter

to be reset when the reference value is reached (reset

at reference). The reference value itself is not reached

though. Additionally, the input signal can be inverted

prior to internal processing and the counting direction

(up/down) be set in most counter modes.

The counters operate synchronously with the SYNC sig-

nal or asynchronously so that the current value is sup-

plied. Some modes do not allow external synchroniza-

tion because the respective synchronization is carried

out internally. This affects the time measurement and

the synchronization triggered by the second channel.

The synchronous mode also allows reading the asyn-

chronous (current) counter value by sending a SYNC

command to the relevant iC via the SPI and reading the

value as regular sensor data. Tab. 21 gives an overview

of usable configuration bits depending on the selected

mode. ’X’ means ’possible’, ’-’ means ’not possible’ (bit

is ignored), ’(-)’ means ’possible but not useful’.

Additionally, the counter allows the generation of a

pulse-width modulated signal in two different modes.

• Simple PWM: The PWM mode is selected and both

16 bit periods t_high and t_ges as in Table 20 and

Figure 6 are written to the reference register. The

PWM can be switched on and off via the process

data. When switched on, it re-starts its period with ’1’.

In addition, the pulse-width can be changed during

run-time by writing the lower half of the reference reg-

ister. In this case, a period that has already started

internally is completed and then the new value is

adopted. When the cycle time is changed, the current

period is terminated immediately and a new period is

started.

• PWM with activation pulse: Unlike in simple PWM

mode, an activation pulse is generated at startup be-

fore the PWM automatically switches to the regular

PWM mode. Note: The registers are interpreted dif-

ferently than the simple PWM mode (see Figure 6). A

change of the pulse width is not intended in this mode.

It is possible though by writing the entire SET_CNT

the simple PWM mode, here the period will not be

completed but starts immediately with a new period.

When the cycle time is changed, the current period is

terminated immediately and a new period is started

without a new activation pulse.

In both modes, the PWM mode supports a high-speed

mode (HS) with a resolution of 125 ns, a cycle time of

up to 8.192 ms and a low-speed mode (LS) with a res-

olution of 16 ns and a cycle time of up to 1.048 s (see

Table 20). The initial pulse may be up to 1 LSB shorter

due to the temporal resolution of the internal clock in

low-speed mode. The reference register can either be

written completely (4 bytes) or only its low-order part

(2 bytes). For simple PWM, the latter complies with a

change of t_high. The PWM then is output at IAx (X =

1, 2). Time t_ges must not be 0x0000.

These following modes are supported by the counters:

Single mode

• Pulse counter: Counts pulses (= rising edges) of the

respective channel.

• Time measurement period: Measures the time be-

tween two rising edges. No external sync possible

because it is synchronized with the rising edge.

• Time measurement pulse width: Measures the

time that the respective channel is high. No exter-

nal sync possible because it is synchronized with the

falling edge.

• Pulse-width modulation: Generates a PWM signal

with a duty cycle depending on REF_CNT_x. The

High-time, cycle time and, if necessary, the activation

pulse time are configurable (see figure 6).

Dual Mode

• Pulse counter with trigger: Counts pulses on CH_1.

CH_2 serves as a trigger to enable the counter value

to be output. The counter value CH_1 is not reset.

Since CH_2 performs the function of synchronization,

no external sync is possible.

IC-GD датащи(PDF) 34 Page - IC-Haus GmbH

IC-GD датащи(HTML) 34 Page - IC-Haus GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

датащи скачать

ссылки URL