IC-GD datasheet(30/55 Pages) ICHAUS

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iC-GD

UNIVERSAL I/O INTERFACE

Rev A1, Page 30/55

STARTUP, RESET, WATCHDOGS

When the supply voltages are applied and VCC ex-

ceeds the undervoltage reset threshold (Vtu(VCC)hi),

the iC-GD starts with the self-configuration. The inter-

nal registers are initialized and the configuration and

calibration data from the EEPROM are read. During

the phase of self-configuration, (RDY = lo), SPI commu-

nication is blocked.

The EEPROM is read via the I2C interface. Here, the

configuration and calibration data are read from the

EEPROM and written into the internal registers. Dur-

ing the entire configuration, a 16-bit CRC checksum

is calculated and compared with the checksum that is

also stored in the EEPROM. If these do not match, the

configuration will be rejected and the chip returns to

its default state. The error status is stored in register

SPV_REG, bit ST_CONF. Also, a 16-bit checksum is

calculated for the calibration data and compared with

the checksum stored in the EEPROM. If those do not

match, only the error status is stored in the register

SPV_REG, bit ST_CALIB. The read data is kept, ex-

cept for the frequency calibration. Additionally, in cer-

tain modes further calibration data from the EEPROM is

read and protected by a separate 8-bit CRC if required.

The iC uses the memory area of the EEPROM shown

in table 13. The subsequent memory area is freely

available to the user.

The chip then provides several possibilities for internal

and external resetting. The cause of the last reset is

stored in a status register.

• Supply voltage: If the supply voltage VCC drops

below the undervoltage reset threshold (Vtu(VCC)lo),

the chip is reset. As stated above, it restarts when

the supply voltage is restored.

• NRES pin: If the NRES pin is low for at least tRESlo,

the chip is reset. Shorter pulses may but do not have

to cause a reset.

• Reset via SPI: The chip can be reset immediately

by writing into the register SPI_LOCK_RESET the

relevant command.

• Watchdog SPI: An internal watchdog timer can be

optionally enabled, to monitor the SPI communication.

If no valid SPI communication takes place during a

certain time period (see table 19), the watchdog re-

sets the iC. A valid communication is one of the

opcodes "PROCESS DATA 1/2/1 and 2".

• Watchdog µC: An internal watchdog monitors the in-

ternal processor. The processor operates the watch-

dog regularly during its main routine. If the watchdog

is not operated within the the µC time-out (see table

19), it resets the iC.

Reset times

Watchdog µC

125 ms ±5 ms

Watchdog SPI 53 ms ±3 ms

Table 19: Watchdogs (times are only valid with cali-

brated oscillator)

SPI

The iC-GD is controlled via an SPI interface. The SPI

interface allows fast reading of measurement data and

the setting of actuator values as well as reading and

writing of configuration registers. The SPI provides a

bridge to the I2C interface and thus also to the con-

nected EEPROM.

The SPI operates synchronously with the supplied clock.

To this end, it samples the input data with the falling

edge and outputs the data with the rising edge. By

default, it outputs the input data with half a clock delay.

The iC is activated by the NCS pin, so that the subse-

quent 8 bits can be interpreted as control code. This

contains a 4-bit opcode, a 3-bit address and a broad-

cast bit. If the iC as such is not addressed, it hibernates

and only relays the input data. Otherwise, it interprets

the opcode.

An additional delay in the signal path (SDO) between

0 and 7 clocks can be set via the configuration bit

EN_UCM. Thus, the total delay of a daisy chain of

up to 8 iCs can be set up to a multiple of 8 clocks. This

has to be carried out in the last iC of the SPI chain.

This iC automatically determines the required number

of clocks of additional delay by means of its address.

This allows proper control by a µC.

The SPI protocol is optimized for the transfer of sensor

and actuator data. Sensor data is available directly fol-

lowing the opcode and can be clocked out subsequently.

Actuator data can be sent directly following the opcode.

To read data from internal registers, a provisioning time

of 8 clocks following the opcode and the address is

required, which can be filled with optional data. To write

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