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HT45F75 датащи(PDF) 62 Page - Holtek Semiconductor Inc |
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HT45F75 датащи(HTML) 62 Page - Holtek Semiconductor Inc |
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62 / 190 page ![]() Rev. 1.10 �� De�e��e� 1�� �01� Rev. 1.10 �3 De�e��e� 1�� �01� HT45F75 Body Fat Scale Flash MCU HT45F75 Body Fat Scale Flash MCU • CTRL Register Bit 7 6 5 4 3 2 1 0 Na�e FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 “x” unknown Bit7 FSYSON:fSYSControlinIDLEMode Describedelsewhere. Bit6~3 Unimplemented,readas“0” Bit2 LVRF:LVRfunctionresetflag 0:Notoccur 1:Occurred ThisbitissethighwhenaspecificLowVoltageResetsituationconditionoccurs.This bitcanonlybeclearedtozerobytheapplicationprogram. Bit1 LRF:LVRControlregistersoftwareresetflag 0:Notoccur 1:Occurred ThisbitissethighiftheLVRCregistercontainsanynon-definedLVRvoltageregister values.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto zerobytheapplicationprogram. Bit0 WRF:WDTControlregistersoftwareresetflag Describedelsewhere. Watchdog Time-out Reset during Normal Operation TheWatchdogtime-outResetduringnormaloperationisthesameasLVRresetexceptthatthe Watchdogtime-outflagTOwillbesethigh. t RS TD + t SST WD T Ti me -o ut In te r nal R es et Note:tRSTDispower-ondelay,typicaltime=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode TheWatchdogtime-outResetduringSLEEPorIDLEModeisalittledifferentfromotherkinds ofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStack PointerwillbeclearedtozeroandtheTOflagwillbesethigh.RefertotheA.C.Characteristicsfor tSSTdetails. t SST WD T Ti me -o ut In te r nal R es et Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbyHIRC. ThetSSTis1024clockforHXTorLXT.ThetSSTis1~2clockforLIRC. WDT Time-out Reset during Sleep or IDLE Mode Timing Chart |
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