HT45F4MA datasheet(98/145 Pages) HOLTEK

98 / 145 page

Rev. 1.20

De�e��e� 1�� 201�

Rev. 1.20

De�e��e� 1�� 201�

HT45F4MA/HT45FH4MA/HT45FH4MA-1

Power Bank Flash MCU

HT45F4MA/HT45FH4MA/HT45FH4MA-1

Power Bank Flash MCU

A/D Operation

TheSTARTbitintheADCR0registerisusedtostartandresettheA/Dconverter.Whenthe

microcontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversion

cyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,the

EOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.

ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigital

converter.

TheEOCBbitintheADCR0registerisusedtoindicatewhentheanalogtodigitalconversion

processiscomplete.Thisbitwillbeautomaticallysetto“0”bythemicrocontrolleraftera

conversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbeset

intheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterrupt

signalwillbegenerated.ThisA/Dinternalinterruptsignalwilldirecttheprogramflowtothe

associatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,

themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithas

beenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosen

tobeeitherfSYSorasubdividedversionoffSYS.Thedivisionratiovalueisdeterminedbythe

ADCK2~ADCK0bitsintheADCR1register.

AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0,

therearesomelimitationsontheA/Dclocksourcespeedrangethatcanbeselected.Asthe

recommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5µsto10µs,caremustbe

takenforselectedsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequency

of4MHz,theADCK2~ADCK0bitsshouldnotbesetto000Bor110B.DoingsowillgiveA/D

clockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/D

clockperiodwhichmayresultininaccurateA/Dconversionvalues.

Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,

dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybeoutoftherecommended

A/Dclockperiodrange.

fSYS

A/D Clock Period (tADCK)

ADCK2,

ADCK1,

ADCK0

=000

(fSYS)

ADCK2,

ADCK1,

ADCK0

=001

(fSYS/2)

ADCK2,

ADCK1,

ADCK0

=010

(fSYS/4)

ADCK2,

ADCK1,

ADCK0

=011

(fSYS/8)

ADCK2,

ADCK1,

ADCK0

=100

(fSYS/16)

ADCK2,

ADCK1,

ADCK0

=101

(fSYS/32)

ADCK2,

ADCK1,

ADCK0

=110

(fSYS/64)

ADCK2,

ADCK1,

ADCK0

=111

1MHz

1μs

2μs

�μs

8μs

1�μs*

32μs*

��μs*

Undefined

2MHz

500ns

1μs

2μs

�μs

8μs

1�μs*

32μs*

Undefined

�MHz

250ns*

500ns

1μs

2μs

�μs

8μs

1�μs*

Undefined

8MHz

125ns*

250ns*

500ns

1μs

2μs

�μs

8μs

Undefined

12MHz

83ns*

1�7ns*

333ns*

��7ns

1.33μs

2.�7μs

5.33μs

Undefined

1�MHz

�2.5ns*

125ns*

250ns*

500ns

1μs

2μs

�μs

Undefined

20MHz

50ns*

100ns*

200ns*

�00ns*

800ns

1.�μs

3.2μs

Undefined

A/D Clock Period Examples

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