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T48C862x-Rf-TNQ датащи(PDF) 40 Page - ATMEL Corporation

номер детали T48C862x-Rf-TNQ
подробное описание детали  Microcontroller with UHF ASK/FSK Transmitter
PDF  107 Pages
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

T48C862x-Rf-TNQ датащи(HTML) 40 Page - ATMEL Corporation

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T48C862-R4 [Preliminary]
4551C–4BMCU–01/04
Figure 33.
UTCM Block Diagram
Timer 1
The Timer 1 is an interval timer which can be used to generate periodical interrupts and
as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL
or SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as
source for the Timer 1 interrupt. Because of other system requirements, the Timer 1 out-
put T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP
(CPU core -> sleep and OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0).
Nevertheless, the Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The
interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit
of the T1C2 register. The time interval for the timer output can be programmed via the
Timer 1 control register T1C1.
Demodu-
lator 3
8-bit Counter 3
Capture 3
Compare 3/1
Compare 3/2
Modu-
lator 3
MUX
MUX
Control
Watchdog
Interval / Prescaler
Timer 1
Timer 3
Modu-
lator 2
4-bit Counter 2/1
Compare 2/1
MUX
MUX
DCG
8-bit Counter 2/2
Compare 2/2
Control
Timer 2
MUX
8-bit shift register
Receive buffer
Transmit buffer
Control
SSI
SCL
INT4
INT5
INT2
NRST
INT3
POUT
TOG2
TOG3
T1OUT
SUBCL
SYSCL
from clock module
T3O
T3I
T2I
T2O
SC
SD
I/O bus



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