T48C862x-Rf-TNQ datasheet(83/107 Pages) ATMEL

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T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Combination Mode 7:

Pulse-width Modulation

(PWM)

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 9: Pulse-width modulation with the shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data

output selects which compare register is used for the output pulse generation. In this

mode, both compare and compare mode registers must be programmed to generate the

two pulse width. It is also useful to enable the single-action mode for extreme duty

cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3.

The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an

internal or external clock source.

Figure 81.

Pulse-width Modulation

Combination Mode 8:

Manchester

Demodulation/Pulse-width

Demodulation

SSI mode 1:

8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3

For Manchester demodulation, the edge detection stage must be programmed to detect

each edge at the input. These edges are evaluated by the demodulator stage. The timer

stage is used to generate the shift clock for the SSI. A compare register 1 match event

defines the correct moment for shifting the state from the input T3I as the decoded bit

into shift register. After that, the demodulator waits for the next edge to synchronize the

timer by a reset for the next bit. The compare register 2 can be used to detect a time

error and handle it with an interrupt routine.

Before activating the demodulator mode the timer and the demodulator stage must be

synchronized with the bitstream. The Manchester code timing consists of parts with the

half bitlength and the complete bitlength. A synchronization routine must start the

demodulator after an interval with the complete bitlength.

The counter can be driven by any internal clock source. The output T3O can be used by

Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demod-

ulation. The input must programmed to detect the positive edge. The demodulator and

timer must be synchronized with the leading edge of the pulse. After that a counter

match with the compare register 1 shifts the state at the input T3I into the shift register.

The next positive edge at the input restarts the timer.

000 00 00 00

000 0

Counter 3

CM31

CM32

T3O

00 0 001 234 56 7 8 9 1011121314150 12 345

TOG2

67 8

91112

2 3

SIR

SCO

T3R

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