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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9658 датащи(PDF) 41 Page - STMicroelectronics |
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L9658 датащи(HTML) 41 Page - STMicroelectronics |
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41 / 64 page  L9658 Functional description Doc ID 14219 Rev 3 41/64 4.11.7 Deployment driver MISO bit definition MISO mode bits are defined as below table. 4.11.8 Deployment driver register mode response Register Mode Response is the default response to the processor. After POR event, RESETB negated, and loss of GND, the device send $0000 in MISO for the first SPI transmission. Register Mode Response is defined as shown in the following table. Table 22. MISO bit layout MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 23. MISO mode bits definition Bit D15 Bit D14 Description 0 0 Register mode response 0 1 Command mode response 1 0 Diagnostic mode response 1 1 Status response/SPI fault response Table 24. MISO register mode response definition Bit State Description D15 0 Mode Bits D14 0 D13 0 Don’t Care D12 - Echo of MOSI Read/Write Bit D11 0 Pulse Stretch Timer Duration 1 Soft Reset Sequence D10 0 Deployment Condition: IDEPLOY_12A and tDEPLOY_2ms 1 Deployment Condition: IDEPLOY_175A and tDEPLOY_1ms D9 - Pulse Stretch timer (see Table 17) D8 - D7 0 Don’t Care D6 0 Don’t Care D5 0 Don’t Care D4 0 Don’t Care D3 0 Don’t Care D2 0 Don’t Care D1 - Hard Reset Status D0 - Soft Reset Sequence Status |
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