L9658 datasheet(21/64 Pages) STMICROELECTRONICS

21 / 64 page

L9658

Functional description

Doc ID 14219 Rev 3

21/64

Figure 9.

Arming SPI transmission

4.8.1

Chip select (CS_A, CS_D, CS_S)

Chip-select inputs select L9658 for serial transfers. CS_A is independent to CS_D and

CS_S.

CS_A can be asserted regardless of CS_D and CS_S. However, either CS_D or CS_S can

be asserted at any given time. If both CS_D and CS_S inputs are selected simultaneously,

the device ignores MOSI command. When chip-select is asserted, the respective

MISO/MISO_A pin is released from tri-state mode, and all status information is latched in

the SPI shift register. While chip-select is asserted, register data is shifted into

MOSI/MOSI_A pin and shifted out of MISO/MISO_A pin on each subsequent

SCLK/SCLK_A. When chip-select is negated, MISO/MISO_A pin is tri-stated. To allow

sufficient time to reload the registers; chip-select pin shall remain negated for at least tCSN.

Chip-select is also immune to spurious pulses of 50 ns or shorter (MISO/MISO_A may

come out of tri-state, but no status bits is cleared and no control bits is changed).

Chip-select inputs have current sinks on the pins, which pull these pins to the negated state

when an open circuit condition occur. These pins have TTL level compatible input voltages

allowing proper operation with microprocessors using a 3.3 to 5.0 V supply.

4.8.2

Serial clock (SCLK, SCLK_A)

SCLK/SCLK_A input is the clock signal input for synchronization of serial data transfer. This

pin has TTL level compatible input voltages allowing proper operation with microprocessors

using a 3.3 to 5.0 V supply. When chip select is asserted, both the SPI master and this

device shall latch input data on the rising edge of SCLK/SCLK_A. L9658 shift data out on

the falling edge of SCLK/SCLK_A. The SCLK/SCLK_A must be taken in idle state (LOW)

when the CS_A,CS_D,CS_S are in idle state (LOW). (a)

4.8.3

Serial data output (MISO, MISO_A)

MISO/MISO_A output pin shall be in a tri-state condition when chip select is negated. When

chip select is asserted, the MSB is the first bit of the word/byte transmitted on

MISO/MISO_A and the LSB is the last bit of the word/byte transmitted. This pin supplies a

rail to rail output, so if interfaced to a microprocessor that is using a lower VDD supply, the

appropriate microprocessor input pin shall not sink more than IOH (min) and shall not clamp

the MISO/MISO_A output voltage to less than VOH (min) while MISO/MISO_A pin is in a

logic “1” state.

IC_1 MISO_A,

IC_2 MOSI_A

µP MOSI,

IC_1 MOSI_A

µP CS,

IC CS_A

IC_3 MISO_A,

µP MOSI

IC_2 MISO_A,

IC_3 MOSI_A

Command #1

Command #2

Command #3

IC_1 Status

Command #1

Command #2

IC_2 Status

IC_1 Status

Command #1

IC_3 Status

MSB

LSB

IC_2 Status

IC_1 Status

Only in daisy chain, it is needed to guarantee on SCLK_A a clock skew of 3ns maximum between any devices.

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