L9658 datasheet(18/64 Pages) STMICROELECTRONICS

18 / 64 page

Functional description

L9658

18/64

Doc ID 14219 Rev 3

Functional description

4.1

Overview

L9658 is an integrated circuit to be used in air bag systems. Its main functions include

deployment of air bags, switched-power sources to satellite sensors, diagnostics of SDM

(Sensing Deployment Module) and arming inputs. L9658 supports 8 deployment loops, 4

satellite-sensor interfaces, and SPI arming inputs.

4.2

Power on reset (POR)

L9658 has a power on reset (POR) circuit, which monitors VDD voltage. When VDD voltage

falls below VRST for longer than or equal to tPOR, all outputs are disabled and all internal

registers are reset to their default condition.

When VDD falls below VRST_L, all outputs are disabled and all internal registers are reset to

their default condition. No delay filter shall be used along with VRST_L threshold.

If VDD voltage falls below VRST for less than tPOR, operation shall not be interrupted.

When VDD rises above VRST, the outputs are enabled. Before VDD reaches VRST, and during

tPOR, none of the outputs turn on.

4.3

RESETB

RESETB pin is active low. The effects of RESETB are similar to those of a POR event,

except during a deployment. When L9658 has a deployment in-progress, it ignores

RESETB signal.

However, it shall shut itself down as soon as it detects a POR condition. When the

deployment is completed and RESETB signal is asserted, the device disables its outputs

and reset its internal registers to their default states.

A de-glitch timer is provided to RESETB pin. The timer protects this pin against spurious

glitches. UT48 neglects RESETB signal if it is asserted for shorter than tGLITCH. RESETB

has an internal pull-up in case of an open circuit. This pin has a de-glitch timer

4.4

MSG

MSG pin is used to reflect FIFO status. Its polarity can be configured and also the strategy

of activation.

Polling mode: Message pin shall be active as soon as one of the 4 FIFO will be not empty

and it will be inactive when all 4 FIFO will be empty. A microcontroller can periodically

monitor the status of line to understand there are data received from satellite. Interrupt

mode: Message pin shall be active as soon one of the 4 FIFO will be not empty and it will be

inactive when a spi communication on CS_S interface starts. At the end of the SPI

communication it shall be active if one of the 4 FIFO will be not empty. Otherwise shall be

kept inactive. A microcontroller can wait until an edge is present on the line and manage the

data available in the FIFO.

L9658 датащи(PDF) 18 Page - STMicroelectronics

L9658 датащи(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

датащи скачать

ссылки URL