L9658 datasheet(17/64 Pages) STMICROELECTRONICS

17 / 64 page

L9658

Electrical specification

Doc ID 14219 Rev 3

17/64

VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V. V8BUCK = 7.0 V to 8.5 V, Tamb = -40° C to +95 °C

All SPI timing is performed with a 200 pF load on MISO unless otherwise noted.

Figure 5.

SPI timing diagram

Figure 6.

SPI timing measurement

Table 11.

SPI timing

No.

Symbol

Parameter

Min

Typ

Max

Unit

fop

Transfer frequency

5.50

MHz

1tSCK

SCLK, SCLK_A Period

181

2tLEAD

Enable lead time

3tLAG

Enable lag time

4tSCLKHS

SCLK, SCLK_A high time

5tSCLKLS

SCLK, SCLK_A low time

6tSUS

MOSI, MOSI_A input setup time

7tHS

MOSI, MOSI_A input hold time

8tA

MISO, MISO_A access time

9tDIS

MISO, MISO_A disable time (1)

100

tVS

MISO, MISO_A output valid time

tHO

MISO, MISO_A output hold time (1)

tRO

Rise Time (Design Information)

tFO

Fall Time (Design Information)

tCSN

CS_A, CS_D, CS_S negated time

640

Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on

the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time,

and minimum capacitance on MISO is the worst case for output hold time.

SCLK

DON'T

CARE

MISO

MOSI

LAG

CSN

SCLKHS

LEAD

SCLKLS

SUS

RO, tFO

DIS

MSB IN

LSB IN

DATA

MSB OUT

LSB OUT

DATA

+5 V

1.0 V

4.0 V

MISO

VDD

MISO

DIS

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