L9658 datasheet(20/64 Pages) STMICROELECTRONICS

20 / 64 page

Functional description

L9658

20/64

Doc ID 14219 Rev 3

Figure 7.

SPI block diagram

L9658 has a counter to verify the number of clocks in SCLK and SCLK_A. If the number of

clocks in SCLK is not equal to 16 clocks while CS_D is asserted, it ignores the SPI message

and send a SPI fault response. If the number of clocks in SCLK is not equal to 64 clocks

while CS_S is asserted, it ignores the entire SPI message and push the Bad SPI Bit Count

fault code into the FIFO. If the number of clocks in SCLK_A is not a multiple of 8, it ignores

the command in the arming shift register. Otherwise, the device latch-in the command.

Figure 8.

Arming daisy-chain configuration

Arming SPI interface is based on 8-bit data transfer. The device is capable to receive a

multiple of 8-bit commands. The first byte of data coming out of MISO_A will be the arming

status bits. The subsequent bits will be the arming command bits received through MOSI_A

pin. Refer to below figure for an example of arming SPI transmission. This is an example of

arming SPI transmission based on the daisy-chain configuration.

In case of daisy chain connection for Arming SPI, device works as following:

All devices IC_1, IC_2, IC_3 shifted out data on the falling edge of SCLK_A for the first 8 bits

and shifted out data on the rising edge of SCLK_A for the bits after 8bits. therefore µP, IC_3,

IC_2 shall strobe 24bits on rising edge of SCLK_A, the first 8 bits are produced (by IC_3,

IC_2, IC_1 respectively) on the falling edge of SCLK_A. the remaining 16 bits are shifted out

on the rising edge.

MISO

MSB

LSB

Control Bits

Status Bits

Input Shift Register

SCLK

MOSI

CS_D

Output Shift Register

vdd

vss

30µA

CS_S

30µA

MISO_A

MSB

LSB

Control Bits

Status Bits

SCLK_A

MOSI_A

CS_A

Shift Register

vdd

vss

30µA

MISO

MOSI

SCLK

MOSI_A

MISO_A

CS_A

SCLK_A

IC_1

IC_3

IC_2

µP

MOSI_A

MISO_A

CS_A

SCLK_A

CS_A

SCLK_A

MOSI_A

MISO_A

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