L9658 datasheet(52/64 Pages) STMICROELECTRONICS

52 / 64 page

Functional description

L9658

52/64

Doc ID 14219 Rev 3

4.14.10

Message waiting

The MSG pin is asserted when there is a message in any of the 4 internal FIFO buffers. This

pin is TTL level and is configurable to be either active high or active low signal.

The Pin shall also be programmable via SPI to either remain active during CS_S once is set

or inactive during CS. IF the pin is configured to remain active during CS_S and there is a

message in any of the internal FIFO it remains active even if CS_S is de-asserted. However

if there are no messages in any of the internal 4 FIFOs the pin will be forced to inactive

state.

4.14.11

Satellite serial data input (MOSI)

The MOSI input takes data from the master microprocessor while CS_S is asserted. The

MSB is the first bit of each word received on MOSI and the LSB is the last bit of each word

received on MOSI. This pin has TTL level compatible input voltages allowing proper

operation with microprocessors using a 3.3 to 5.0 volt supply. MOSI Bits layout is provided

here below.

4.14.12

Satellite MOSI bits definition

There are total of 5 internal registers that are used to configure all of the satellite channels.

These registers are addressed by setting MOSI bit 14 according to this table and by sending

the SPI commands sequentially in the correct order such that CH1 command is the first

significant word and CH4 command is the Last word.

The SPI command sequence is such that the first word communicates with channel 1, the

second SPI word communicates with channel 2, the third SPI word is in communication with

channel 3 and the 4th word with channel 4.

Table 32.

Satellite MOSI bits layout

87654

3210

DATA (12:0)

Table 33.

MOSI satellite interface registers map

Bit

State

Description

D15

SPI Odd Parity

D14

MCR Master Configuration Register (CH1 Only)

CCR1 Channel Configuration Register for CH1

CCR2 Channel Configuration Register for CH2

CCR3 Channel Configuration Register for CH3

CCR4 Channel Configuration Register for CH4

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