ST72561AR7-Auto datasheet(99/324 Pages) STMICROELECTRONICS

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ST72561-Auto

PWM auto-reload timer (ART)

Doc ID 12370 Rev 8

99/324

11.3

Control/status register (ARTCSR)

Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = EXCL External Clock

This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler.

0: CPU clock.

1: External clock.

Bit 6:4 = CC[2:0] Counter Clock Control

These bits are set and cleared by software. They determine the prescaler division ratio from

fINPUT.

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the timer in the lowest power consumption

mode.

0: Counter stopped (prescaler and counter frozen).

1: Counter running.

Bit 2 = FCRL Force Counter Re-Load

This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes

the contents of ARTARR register to be loaded into the counter, and the content of the

prescaler register to be cleared in order to initialize the timer before starting to count.

Bit 1 = OIE Overflow Interrupt Enable

This bit is set and cleared by software. It allows to enable/disable the interrupt which is

generated when the OVF bit is set.

0: Overflow Interrupt disable.

1: Overflow Interrupt enable.

EXCL

CC2

CC1

CC0

TCE

FCRL

OIE

OVF

Table 43.

Counter clock control

fCOUNTER

With fINPUT=8 MHz

CC2

CC1

CC0

fINPUT

fINPUT / 2

fINPUT / 4

fINPUT / 8

fINPUT / 16

fINPUT / 32

fINPUT / 64

fINPUT / 128

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

250 kHz

125 kHz

62.5 kHz

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