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ST72561AR7-Auto датащи(PDF) 101 Page - STMicroelectronics

номер детали ST72561AR7-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561AR7-Auto датащи(HTML) 101 Page - STMicroelectronics

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ST72561-Auto
PWM auto-reload timer (ART)
Doc ID 12370 Rev 8
101/324
PWM control register (PWMCR)
Read/write
Reset value: 0000 0000 (00h)
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM output
channels independently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity of the
four PWM output signals.
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately
reversed.
Duty cycle registers (PWMDCRx)
Read/write
Reset value: 0000 0000 (00h)
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx register of each PWM channel to
determine the second edge location of the PWM signal (the first edge location is common to
all channels and given by the ARTARR register). These PWMDCR registers allow the duty
cycle to be set independently for each PWM channel.
Input Capture control / status register (ARTICCSR)
Read/Write
Reset value: 0000 0000 (00h)
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
Table 45.
PWMx output level and polarity
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
10
0
01
1
7
0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0



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