ST72561AR7-Auto datasheet(94/324 Pages) STMICROELECTRONICS

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PWM auto-reload timer (ART)

ST72561-Auto

94/324

Doc ID 12370 Rev 8

11.2

Functional description

11.2.1

Counter

The free running 8-bit counter is fed by the output of the prescaler, and is incremented on

every rising edge of the clock signal.

It is possible to read or write the contents of the counter on the fly by reading or writing the

Counter Access register (ARTCAR).

When a counter overflow occurs, the counter is automatically reloaded with the contents of

the ARTARR register (the prescaler is not affected).

11.2.2

Counter clock and prescaler

The counter clock frequency is given by:

fCOUNTER = fINPUT / 2

CC[2:0]

The timer counter’s input clock (fINPUT) feeds the 7-bit programmable prescaler, which

selects one of the eight available taps of the prescaler, as defined by CC[2:0] bits in the

Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2n

(where n = 0, 1...7).

This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and

can be either the fCPU or an external input frequency fEXT.

The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the

ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter

contents are frozen. When TCE is set, the counter runs at the rate of the selected clock

source.

11.2.3

Counter and prescaler Initialization

After RESET, the counter and the prescaler are cleared and fINPUT = fCPU.

The counter can be initialized by:

●

Writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load)

and the TCE (Timer Counter Enable) bits in the ARTCSR register.

●

Writing to the ARTCAR counter access register,

In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known

value.

Direct access to the prescaler is not possible.

11.2.4

Output compare control

The timer compare function is based on four different comparisons with the counter (one for

each PWMx output). Each comparison is made between the counter value and an output

compare register (OCRx) value. This OCRx register can not be accessed directly, it is

loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.

This double buffering method avoids glitch generation when changing the duty cycle on the

fly.

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