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ST72561AR7-Auto датащи(PDF) 66 Page - STMicroelectronics

номер детали ST72561AR7-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561AR7-Auto датащи(HTML) 66 Page - STMicroelectronics

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Power saving modes
ST72561-Auto
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Doc ID 12370 Rev 8
system is enabled, can generate a Watchdog RESET (see Section 22.1: Introduction for
more details).
Figure 25.
HALT timing overview
Figure 26.
HALT mode flow-chart
Note:
1
WDGHALT is an option bit. See option byte section for more details.
2
Peripheral clocked with an external clock source can still be active.
3
Only some specific interrupts can exit the MCU from HALT mode (such as external
interrupt). Refer to Table 16 for more details.
4
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
HALT
RUN
RUN
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[MCCSR.OIE=0]
RESET
INTERRUPT 3)
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
I[1:0] BITS
OFF
OFF
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
OFF
XX 4)
ON
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
ON
XX 4)
ON
256 OR 4096 CPU CLOCK
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1)
0
WATCHDOG
RESET
1
CYCLE
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=0)



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