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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72561AR7-Auto датащи(PDF) 84 Page - STMicroelectronics |
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ST72561AR7-Auto датащи(HTML) 84 Page - STMicroelectronics |
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84 / 324 page  Window watchdog (WWDG) ST72561-Auto 84/324 Doc ID 12370 Rev 8 9.4 Using halt mode with the WDG If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. 9.5 How to program the watchdog timeout Figure 35 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 36. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 35. Approximate timeout duration Watchdog timeout (ms) @ 8 MHz fOSC2 3F 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 |
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