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ST72561AR7-Auto датащи(PDF) 102 Page - STMicroelectronics

номер детали ST72561AR7-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561AR7-Auto датащи(HTML) 102 Page - STMicroelectronics

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PWM auto-reload timer (ART)
ST72561-Auto
102/324
Doc ID 12370 Rev 8
Bit 7:6 = Reserved, always read as 0.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They determine the trigger event polarity on the
corresponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They enable or disable the Input capture
channel interrupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by software reading the corresponding
ARTICRx register. Each CFx bit indicates that an input capture x has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
Input Capture Registers (ARTICRx)
Read only
Reset value: 0000 0000 (00h)
Bit 7:0 = IC[7:0] Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-
bit auto-reload counter value transferred by the input capture channel x event.
7
0
0
0
CS2
CS1
CIE2
CIE1
CF2
CF1
7
0
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
Table 46.
PWM auto-reload timer register map and reset values
Address
(Hex.)
Register label
7
6
5
4
3
2
1
0
0031h
PWMDCR3
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0032h
PWMDCR2
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0033h
PWMDCR1
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0034h
PWMDCR0
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0



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