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ST72561AR7-Auto датащи(PDF) 41 Page - STMicroelectronics

номер детали ST72561AR7-Auto
подробное описание детали  Clock, reset and supply management
PDF  324 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561AR7-Auto датащи(HTML) 41 Page - STMicroelectronics

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ST72561-Auto
Supply, reset and clock management
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5
Supply, reset and clock management
5.1
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example, in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 11.
For more details, refer to dedicated parametric section.
5.2
Main features
Optional PLL for multiplying the frequency by 2
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
4 Crystal/Ceramic resonator oscillators
System Integrity Management (SI)
Main supply Low voltage detection (LVD)
Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main
supply
5.3
Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option
byte. If the PLL is disabled, then fOSC2 =fOSC/2.
Caution:
The PLL is not recommended for applications where timing accuracy is required.
Section 20.5.2: PLL characteristics
Figure 10.
PLL block diagram
0
1
PLL OPTION BIT
PLL x 2
fOSC2
/ 2
fOSC



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