ST72561J4-Auto datasheet(114/324 Pages) STMICROELECTRONICS

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16-bit timer

ST72561-Auto

114/324

Doc ID 12370 Rev 8

Select the following in the CR2 register:

–

Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1

function.

–

Set the OPM bit.

–

Select the timer clock CC[1:0] (see Table 50).

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is

loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the

ICIE bit is set.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two

steps:

Reading the SR register while the ICFi bit is set.

An access (read or write) to the ICiLR register.

The OC1R register value required for a specific timing application can be calculated using

the following formula:

Where:

= Pulse period (in seconds)

fCPU

CPU clock frequency (in hertz)

PRESC =

Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 50)

If the timer clock is an external clock the formula is:

Where:

Pulse period (in seconds)

fEXT

External timer clock frequency (in hertz)

When the value of the counter is equal to the value of the contents of the OC1R register, the

OLVL1 bit is output on the OCMP1 pin, (See Figure 57).

event occurs

Counter

= OC1R

OCMP1 = OLVL1

When

on ICAP1

One Pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

OCiR Value =

t * fCPU

PRESC

- 5

OCiR =

t * fEXT -5

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