ST72561J4-Auto datasheet(117/324 Pages) STMICROELECTRONICS

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ST72561-Auto

16-bit timer

Doc ID 12370 Rev 8

117/324

fEXT

External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 58)

Note:

After a write instruction to the OCiHR register, the output compare function is inhibited until

the OCiLR register is also written.

The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be

set and IC2R can be loaded) but the user must take care that the counter is reset each

period and ICF1 can also generates interrupt if ICIE is set.

When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

12.4

Low power modes

12.5

Interrupts

Table 47.

Effect of low power modes on 16-bit timer

Mode

Description

WAIT

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes

from the previous count when the MCU is woken up by an interrupt with “exit from HALT

mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is

armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT

mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT

mode is captured into the ICiR register.

Table 48.

Timer interrupt control and wake-up capability

Interrupt event

Event

flag

Enable

control

bit

Exit

from

wait

Exit

from

halt

Input Capture 1 event/Counter reset in PWM mode

ICF1

ICIE

Yes

Input Capture 2 event

ICF2

Output Compare 1 event (not available in PWM mode)

OCF1

OCIE

Output Compare 2 event (not available in PWM mode)

OCF2

Timer Overflow event

TOF

TOIE

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