ST72561J4-Auto datasheet(112/324 Pages) STMICROELECTRONICS

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16-bit timer

ST72561-Auto

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Doc ID 12370 Rev 8

The following procedure is recommended to prevent the OCFi bit from being set between

the time it is read and the write to the OCiR register:

●

Write to the OCiHR register (further compares are inhibited).

●

Read the SR register (first step of the clearance of the OCFi bit, which may be already

set).

●

Write to the OCiLR register (enables the output compare function and clears the OCFi

bit).

Note:

After a processor write cycle to the OCiHR register, the output compare function is inhibited

until the OCiLR register is also written.

If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt could be generated if the OCIE bit is set.

When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the

OCiR register value (see Figure 55). This behavior is the same in OPM or PWM mode.

When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR register value (see Figure 56).

The output compare functions can be used both for generating external events on the

OCMPi pins even if the input capture mode is also used.

The value in the 16-bit OCiR register and the OLVi bit should be changed after each

successful comparison in order to control an output waveform or establish a new elapsed

timeout.

12.3.7

Forced compare output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit

has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The

OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both One Pulse mode and PWM mode.

Figure 54.

Output compare block diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E

CC0

CC1

OC2E

OLVL1

OLVL2

OCIE

(Control Register 1) CR1

(Control Register 2) CR2

OCF2

OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

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