ST72344S2 datasheet(170/247 Pages) STMICROELECTRONICS

170 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

170/247

Doc ID 12321 Rev 6

The Byte count register is reset when it reaches 256 bytes, whatever the page length, for all

slave addresses, including slave 3.

DMA

The I2C slaves use a DMA controller to write/read data to/from their RAM buffer.

A DMA request is issued to the DMA controller on reception of a byte or just before

transmission of a byte.

When a byte is written by DMA in RAM, the CPU is stalled for max. 2 cycles. When several

bytes are transferred from the I2C bus to RAM, the DMA releases between each byte and

the CPU resumes processing until the DMA writes the next byte.

RAM buffer write protection

By setting the WP1/WP2 bits in the I2C3SCR2 register, it is possible to protect the RAM

buffer of Slaves 1/2 respectively against write access from the master.

If a write operation is attempted, the slave address is acknowledged, the current address

current address and byte count registers are incremented as in normal operation.

In case of write access to a write protected address, no interrupt is generated and the

BusyW bit in the I2C3SCR2 register is not set.

Only write operations are disabled/enabled. Read operations are not affected.

Byte-pair coherency for I2C read operations

Byte-pair coherency allows the I2C master to read a 16-bit word and ensures that it is not

corrupted by a simultaneous CPU update. Two mechanisms are implemented, covering the

two possible cases:

CPU updates a word in RAM after the first byte has been transferred to the I2C shift

old word and 2nd byte would be the LSB of the new word.

To prevent this corruption, the I2C3S uses DMA to systematically read a 2-byte word

when it receives a read command from the I2C master. The MSB of the word should be

at address 2n. Using DMA, the MSB is moved from RAM address 2n to the I2C shift

peripheral. The CPU is stalled for a maximum of 2 cycles during word transfer.

In case only one byte is read, the unused content of the shadow register will be

automatically overwritten when a new read operation is performed.

In case a second byte is read in the same I2C message (no Stop or Restart condition),

the content of the shadow register is transferred to the shift register and transmitted to

the master.

This process continues until a Stop or Restart condition occurs.

I2C3S attempts to read a word while the CPU is updating the RAM buffer. To prevent

data corruption, the CPU must switch operation to Word mode prior to updating a word

in the RAM buffer. Word mode is enabled by software using the B/W bit in the

I2C3SCR2 register. In Word mode, when the CPU writes the MSB of a word to address

2n, it is stored in a shadow register rather than being actually written in RAM. When the

CPU writes the second byte (the LSB) at address 2n+1, it is directly written in RAM.

The next cycle after the write to address 2n+1, the MSB is automatically written from

the shadow register to RAM address 2n. DMA is disabled for a 1 cycle while the CPU is

writing a word.

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