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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72344S2 датащи(PDF) 50 Page - STMicroelectronics |
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ST72344S2 датащи(HTML) 50 Page - STMicroelectronics |
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50 / 247 page  Supply, reset and clock management ST72344xx, ST2345xx 50/247 Doc ID 12321 Rev 6 In the case of a drop in voltage below VIT-(AVD), the AVDF flag is set and an interrupt request is issued. If VDD rises above the VIT+(AVD) threshold voltage the AVDF bit is cleared automatically by hardware. No interrupt is generated, and therefore software should poll the AVDF bit to detect when the voltage has risen, and resume normal processing. Figure 19. Using the AVD to monitor VDD 7.6.3 Low-power modes 7.6.4 Interrupts The AVD interrupt event generates an interrupt if the corresponding AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction). VDD VIT-(AVD) AVDF bit 0 RESET VALUE IF AVDIE bit = 1 AVD INTERRUPT REQUEST INTERRUPT PROCESS VIT-(LVD) LVD RESET Early warning interrupt (Power has dropped, MCU not not yet in reset) 1 0 1 VIT+(AVD) Vhys Table 10. Low-power mode description Mode Description Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. Halt The SICSR register is frozen. Table 11. Interrupt event Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No |
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