ST72344S2 datasheet(65/247 Pages) STMICROELECTRONICS

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ST72344xx, ST2345xx

Power-saving modes

Doc ID 12321 Rev 6

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9.2

Slow mode

This mode has two targets:

●

To reduce power consumption by decreasing the internal clock in the device,

●

To adapt the internal clock frequency (fCPU) to the available supply voltage.

Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or

disables Slow mode and two CPx bits which select the internal slow frequency (fCPU).

In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU

and peripherals are clocked at this lower frequency (fCPU).

Note:

Slow-wait mode is activated by entering Wait mode while the device is in Slow mode.

Figure 26.

Slow mode clock transitions

9.3

Wait mode

Wait mode places the MCU in a low-power consumption mode by stopping the CPU.

This power saving mode is selected by calling the ‘WFI’ instruction.

All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced

to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU

remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter

branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake

up. Refer to Figure 27.

SMS

CP1:0

fCPU

New slow

Normal Run mode

frequency

request

fOSC2

fOSC2/2

fOSC2/4

fOSC2

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