ST72344S2 datasheet(51/247 Pages) STMICROELECTRONICS

51 / 247 page

ST72344xx, ST2345xx

Supply, reset and clock management

Doc ID 12321 Rev 6

51/247

7.6.5

System integrity (SI) control/status register (SICSR)

Reset value: 000x 000x (xxh)

Bit 7 = Reserved, must be kept cleared.

Bit 6 = AVDIE Voltage detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag goes from 0 to 1. The pending interrupt information is automatically cleared

when software enters the AVD interrupt routine.

0: PDVD interrupt disabled

1: PDVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit goes from 0 to 1. Refer to Figure 19 and to

Section 7.6.2 for additional details.

0: VDD over VIT+(AVD) threshold

1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag

description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set automatically when the PLL reaches its

operating frequency.

0: PLL not locked

1: PLL locked

Bits 2:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is

set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD

Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given by the following

table.

PDVDIE

AVDF

LVDRF

LOCKED

WDGRF

Read/Write

Table 12.

LVDRF and WDGRF description

Reset sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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