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ST72344S2 датащи(PDF) 168 Page - STMicroelectronics |
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ST72344S2 датащи(HTML) 168 Page - STMicroelectronics |
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168 / 247 page ![]() On-chip peripherals ST72344xx, ST2345xx 168/247 Doc ID 12321 Rev 6 Figure 71. I2C3S interface block diagram 11.7.3 General description In addition to receiving and transmitting data, I2C3S converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The I2C3S is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected both with a standard I2C bus and a Fast I2C bus. The interface operates only in Slave mode as transmitter/receiver. In order to fully emulate standard I2C EEPROM devices with highest transfer speed, the peripheral prevents I2C clock signal stretching and performs data transfer between the shift register and the RAM buffers using DMA. Communication flow A serial data transfer normally begins with a start condition and ends with a stop condition. Both start and stop conditions are generated by an external master. Refer to Figure 67 for the standard protocol. The I2C3S is not a master and is not capable of generating a start/stop condition on the SDA line. The I2C3S is capable of recognizing 3 slave addresses which are user programmable. The three I2C slave addresses can be individually enabled/disabled by software. Since the I2C3S interface always acts as a slave, it does not generate a clock. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition contains the slave address. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. I2C SLAVE ADDRESS 1 I2C SLAVE ADDRESS 2 I2C SLAVE ADDRESS 3 CPU RAM 128 BYTES SLAVE 3 BUFFER 256 BYTES SLAVE 1 BUFFER 256 BYTES SLAVE 2 BUFFER DMA COMPARATOR CONTROL LOGIC 8-BIT SHIFT REGISTER SCL or SCLI SDA or SDAI Slave 1 or 2 Interrupt Slave 3 Interrupt DATA E2PROM 256 BYTES REGISTER SHADOW |
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